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linux-next/drivers/clk/uniphier/clk-uniphier-mux.c
Colin Ian King f6b1340dc7 clk: uniphier: Fix potential infinite loop
The for-loop iterates with a u8 loop counter i and compares this
with the loop upper limit of num_parents that is an int type.
There is a potential infinite loop if num_parents is larger than
the u8 loop counter. Fix this by making the loop counter the same
type as num_parents.  Also make num_parents an unsigned int to
match the return type of the call to clk_hw_get_num_parents.

Addresses-Coverity: ("Infinite loop")
Fixes: 734d82f4a6 ("clk: uniphier: add core support code for UniPhier clock driver")
Signed-off-by: Colin Ian King <colin.king@canonical.com>
Reviewed-by: Masahiro Yamada <masahiroy@kernel.org>
Link: https://lore.kernel.org/r/20210409090104.629722-1-colin.king@canonical.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-04-12 19:09:59 -07:00

87 lines
2.0 KiB
C

// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Copyright (C) 2016 Socionext Inc.
* Author: Masahiro Yamada <yamada.masahiro@socionext.com>
*/
#include <linux/clk-provider.h>
#include <linux/device.h>
#include <linux/regmap.h>
#include "clk-uniphier.h"
struct uniphier_clk_mux {
struct clk_hw hw;
struct regmap *regmap;
unsigned int reg;
const unsigned int *masks;
const unsigned int *vals;
};
#define to_uniphier_clk_mux(_hw) container_of(_hw, struct uniphier_clk_mux, hw)
static int uniphier_clk_mux_set_parent(struct clk_hw *hw, u8 index)
{
struct uniphier_clk_mux *mux = to_uniphier_clk_mux(hw);
return regmap_write_bits(mux->regmap, mux->reg, mux->masks[index],
mux->vals[index]);
}
static u8 uniphier_clk_mux_get_parent(struct clk_hw *hw)
{
struct uniphier_clk_mux *mux = to_uniphier_clk_mux(hw);
unsigned int num_parents = clk_hw_get_num_parents(hw);
int ret;
unsigned int val;
unsigned int i;
ret = regmap_read(mux->regmap, mux->reg, &val);
if (ret)
return ret;
for (i = 0; i < num_parents; i++)
if ((mux->masks[i] & val) == mux->vals[i])
return i;
return -EINVAL;
}
static const struct clk_ops uniphier_clk_mux_ops = {
.determine_rate = __clk_mux_determine_rate,
.set_parent = uniphier_clk_mux_set_parent,
.get_parent = uniphier_clk_mux_get_parent,
};
struct clk_hw *uniphier_clk_register_mux(struct device *dev,
struct regmap *regmap,
const char *name,
const struct uniphier_clk_mux_data *data)
{
struct uniphier_clk_mux *mux;
struct clk_init_data init;
int ret;
mux = devm_kzalloc(dev, sizeof(*mux), GFP_KERNEL);
if (!mux)
return ERR_PTR(-ENOMEM);
init.name = name;
init.ops = &uniphier_clk_mux_ops;
init.flags = CLK_SET_RATE_PARENT;
init.parent_names = data->parent_names;
init.num_parents = data->num_parents;
mux->regmap = regmap;
mux->reg = data->reg;
mux->masks = data->masks;
mux->vals = data->vals;
mux->hw.init = &init;
ret = devm_clk_hw_register(dev, &mux->hw);
if (ret)
return ERR_PTR(ret);
return &mux->hw;
}