mirror of
https://github.com/edk2-porting/linux-next.git
synced 2024-12-27 14:43:58 +08:00
39ec748f71
There are still some mysteries left, in particular how (and in fact if) the EDID is supposed to work on the HDMI port. However the basic stuff now works and I can plug my Q550 into an HDMI display and get the expected results. [v2: cleans up space/tab and other formatting as per Dave's request] Signed-off-by: Alan Cox <alan@linux.intel.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
258 lines
8.0 KiB
C
258 lines
8.0 KiB
C
/**************************************************************************
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* Copyright (c) 2007-2011, Intel Corporation.
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* All Rights Reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
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*
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**************************************************************************/
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/* MID device specific descriptors */
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struct oaktrail_timing_info {
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u16 pixel_clock;
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u8 hactive_lo;
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u8 hblank_lo;
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u8 hblank_hi:4;
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u8 hactive_hi:4;
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u8 vactive_lo;
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u8 vblank_lo;
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u8 vblank_hi:4;
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u8 vactive_hi:4;
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u8 hsync_offset_lo;
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u8 hsync_pulse_width_lo;
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u8 vsync_pulse_width_lo:4;
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u8 vsync_offset_lo:4;
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u8 vsync_pulse_width_hi:2;
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u8 vsync_offset_hi:2;
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u8 hsync_pulse_width_hi:2;
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u8 hsync_offset_hi:2;
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u8 width_mm_lo;
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u8 height_mm_lo;
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u8 height_mm_hi:4;
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u8 width_mm_hi:4;
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u8 hborder;
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u8 vborder;
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u8 unknown0:1;
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u8 hsync_positive:1;
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u8 vsync_positive:1;
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u8 separate_sync:2;
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u8 stereo:1;
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u8 unknown6:1;
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u8 interlaced:1;
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} __packed;
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struct gct_r10_timing_info {
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u16 pixel_clock;
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u32 hactive_lo:8;
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u32 hactive_hi:4;
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u32 hblank_lo:8;
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u32 hblank_hi:4;
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u32 hsync_offset_lo:8;
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u16 hsync_offset_hi:2;
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u16 hsync_pulse_width_lo:8;
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u16 hsync_pulse_width_hi:2;
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u16 hsync_positive:1;
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u16 rsvd_1:3;
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u8 vactive_lo:8;
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u16 vactive_hi:4;
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u16 vblank_lo:8;
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u16 vblank_hi:4;
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u16 vsync_offset_lo:4;
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u16 vsync_offset_hi:2;
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u16 vsync_pulse_width_lo:4;
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u16 vsync_pulse_width_hi:2;
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u16 vsync_positive:1;
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u16 rsvd_2:3;
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} __packed;
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struct oaktrail_panel_descriptor_v1 {
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u32 Panel_Port_Control; /* 1 dword, Register 0x61180 if LVDS */
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/* 0x61190 if MIPI */
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u32 Panel_Power_On_Sequencing;/*1 dword,Register 0x61208,*/
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u32 Panel_Power_Off_Sequencing;/*1 dword,Register 0x6120C,*/
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u32 Panel_Power_Cycle_Delay_and_Reference_Divisor;/* 1 dword */
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/* Register 0x61210 */
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struct oaktrail_timing_info DTD;/*18 bytes, Standard definition */
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u16 Panel_Backlight_Inverter_Descriptor;/* 16 bits, as follows */
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/* Bit 0, Frequency, 15 bits,0 - 32767Hz */
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/* Bit 15, Polarity, 1 bit, 0: Normal, 1: Inverted */
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u16 Panel_MIPI_Display_Descriptor;
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/*16 bits, Defined as follows: */
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/* if MIPI, 0x0000 if LVDS */
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/* Bit 0, Type, 2 bits, */
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/* 0: Type-1, */
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/* 1: Type-2, */
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/* 2: Type-3, */
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/* 3: Type-4 */
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/* Bit 2, Pixel Format, 4 bits */
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/* Bit0: 16bpp (not supported in LNC), */
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/* Bit1: 18bpp loosely packed, */
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/* Bit2: 18bpp packed, */
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/* Bit3: 24bpp */
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/* Bit 6, Reserved, 2 bits, 00b */
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/* Bit 8, Minimum Supported Frame Rate, 6 bits, 0 - 63Hz */
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/* Bit 14, Reserved, 2 bits, 00b */
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} __packed;
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struct oaktrail_panel_descriptor_v2 {
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u32 Panel_Port_Control; /* 1 dword, Register 0x61180 if LVDS */
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/* 0x61190 if MIPI */
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u32 Panel_Power_On_Sequencing;/*1 dword,Register 0x61208,*/
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u32 Panel_Power_Off_Sequencing;/*1 dword,Register 0x6120C,*/
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u8 Panel_Power_Cycle_Delay_and_Reference_Divisor;/* 1 byte */
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/* Register 0x61210 */
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struct oaktrail_timing_info DTD;/*18 bytes, Standard definition */
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u16 Panel_Backlight_Inverter_Descriptor;/*16 bits, as follows*/
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/*Bit 0, Frequency, 16 bits, 0 - 32767Hz*/
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u8 Panel_Initial_Brightness;/* [7:0] 0 - 100% */
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/*Bit 7, Polarity, 1 bit,0: Normal, 1: Inverted*/
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u16 Panel_MIPI_Display_Descriptor;
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/*16 bits, Defined as follows: */
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/* if MIPI, 0x0000 if LVDS */
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/* Bit 0, Type, 2 bits, */
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/* 0: Type-1, */
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/* 1: Type-2, */
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/* 2: Type-3, */
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/* 3: Type-4 */
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/* Bit 2, Pixel Format, 4 bits */
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/* Bit0: 16bpp (not supported in LNC), */
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/* Bit1: 18bpp loosely packed, */
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/* Bit2: 18bpp packed, */
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/* Bit3: 24bpp */
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/* Bit 6, Reserved, 2 bits, 00b */
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/* Bit 8, Minimum Supported Frame Rate, 6 bits, 0 - 63Hz */
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/* Bit 14, Reserved, 2 bits, 00b */
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} __packed;
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union oaktrail_panel_rx {
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struct {
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u16 NumberOfLanes:2; /*Num of Lanes, 2 bits,0 = 1 lane,*/
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/* 1 = 2 lanes, 2 = 3 lanes, 3 = 4 lanes. */
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u16 MaxLaneFreq:3; /* 0: 100MHz, 1: 200MHz, 2: 300MHz, */
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/*3: 400MHz, 4: 500MHz, 5: 600MHz, 6: 700MHz, 7: 800MHz.*/
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u16 SupportedVideoTransferMode:2; /*0: Non-burst only */
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/* 1: Burst and non-burst */
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/* 2/3: Reserved */
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u16 HSClkBehavior:1; /*0: Continuous, 1: Non-continuous*/
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u16 DuoDisplaySupport:1; /*1 bit,0: No, 1: Yes*/
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u16 ECC_ChecksumCapabilities:1;/*1 bit,0: No, 1: Yes*/
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u16 BidirectionalCommunication:1;/*1 bit,0: No, 1: Yes */
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u16 Rsvd:5;/*5 bits,00000b */
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} panelrx;
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u16 panel_receiver;
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} __packed;
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struct gct_r0 {
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union { /*8 bits,Defined as follows: */
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struct {
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u8 PanelType:4; /*4 bits, Bit field for panels*/
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/* 0 - 3: 0 = LVDS, 1 = MIPI*/
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/*2 bits,Specifies which of the*/
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u8 BootPanelIndex:2;
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/* 4 panels to use by default*/
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u8 BootMIPI_DSI_RxIndex:2;/*Specifies which of*/
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/* the 4 MIPI DSI receivers to use*/
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} PD;
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u8 PanelDescriptor;
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};
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struct oaktrail_panel_descriptor_v1 panel[4];/*panel descrs,38 bytes each*/
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union oaktrail_panel_rx panelrx[4]; /* panel receivers*/
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} __packed;
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struct gct_r1 {
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union { /*8 bits,Defined as follows: */
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struct {
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u8 PanelType:4; /*4 bits, Bit field for panels*/
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/* 0 - 3: 0 = LVDS, 1 = MIPI*/
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/*2 bits,Specifies which of the*/
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u8 BootPanelIndex:2;
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/* 4 panels to use by default*/
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u8 BootMIPI_DSI_RxIndex:2;/*Specifies which of*/
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/* the 4 MIPI DSI receivers to use*/
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} PD;
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u8 PanelDescriptor;
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};
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struct oaktrail_panel_descriptor_v2 panel[4];/*panel descrs,38 bytes each*/
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union oaktrail_panel_rx panelrx[4]; /* panel receivers*/
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} __packed;
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struct gct_r10 {
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struct gct_r10_timing_info DTD;
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u16 Panel_MIPI_Display_Descriptor;
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u16 Panel_MIPI_Receiver_Descriptor;
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u16 Panel_Backlight_Inverter_Descriptor;
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u8 Panel_Initial_Brightness;
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u32 MIPI_Ctlr_Init_ptr;
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u32 MIPI_Panel_Init_ptr;
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} __packed;
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struct oaktrail_gct_data {
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u8 bpi; /* boot panel index, number of panel used during boot */
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u8 pt; /* panel type, 4 bit field, 0=lvds, 1=mipi */
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struct oaktrail_timing_info DTD; /* timing info for the selected panel */
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u32 Panel_Port_Control;
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u32 PP_On_Sequencing;/*1 dword,Register 0x61208,*/
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u32 PP_Off_Sequencing;/*1 dword,Register 0x6120C,*/
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u32 PP_Cycle_Delay;
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u16 Panel_Backlight_Inverter_Descriptor;
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u16 Panel_MIPI_Display_Descriptor;
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} __packed;
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#define MODE_SETTING_IN_CRTC 0x1
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#define MODE_SETTING_IN_ENCODER 0x2
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#define MODE_SETTING_ON_GOING 0x3
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#define MODE_SETTING_IN_DSR 0x4
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#define MODE_SETTING_ENCODER_DONE 0x8
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/*
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* Moorestown HDMI interfaces
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*/
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struct oaktrail_hdmi_dev {
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struct pci_dev *dev;
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void __iomem *regs;
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unsigned int mmio, mmio_len;
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int dpms_mode;
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struct hdmi_i2c_dev *i2c_dev;
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/* register state */
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u32 saveDPLL_CTRL;
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u32 saveDPLL_DIV_CTRL;
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u32 saveDPLL_ADJUST;
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u32 saveDPLL_UPDATE;
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u32 saveDPLL_CLK_ENABLE;
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u32 savePCH_HTOTAL_B;
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u32 savePCH_HBLANK_B;
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u32 savePCH_HSYNC_B;
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u32 savePCH_VTOTAL_B;
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u32 savePCH_VBLANK_B;
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u32 savePCH_VSYNC_B;
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u32 savePCH_PIPEBCONF;
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u32 savePCH_PIPEBSRC;
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};
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extern void oaktrail_hdmi_setup(struct drm_device *dev);
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extern void oaktrail_hdmi_teardown(struct drm_device *dev);
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extern int oaktrail_hdmi_i2c_init(struct pci_dev *dev);
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extern void oaktrail_hdmi_i2c_exit(struct pci_dev *dev);
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extern void oaktrail_hdmi_save(struct drm_device *dev);
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extern void oaktrail_hdmi_restore(struct drm_device *dev);
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extern void oaktrail_hdmi_init(struct drm_device *dev, struct psb_intel_mode_device *mode_dev);
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extern int oaktrail_crtc_hdmi_mode_set(struct drm_crtc *crtc, struct drm_display_mode *mode,
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struct drm_display_mode *adjusted_mode, int x, int y,
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struct drm_framebuffer *old_fb);
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extern void oaktrail_crtc_hdmi_dpms(struct drm_crtc *crtc, int mode);
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