mirror of
https://github.com/edk2-porting/linux-next.git
synced 2024-12-22 20:23:57 +08:00
876611c493
This patch implements the basic functions of the BMC chip for some Intel FPGA PCIe Acceleration Cards (PAC). The BMC is implemented using the Intel MAX 10 CPLD. This BMC chip is connected to the FPGA by a SPI bus. To provide direct register access from the FPGA, the "SPI slave to Avalon Master Bridge" (spi-avmm) IP is integrated in the chip. It converts encoded streams of bytes from the host to the internal register read/write on the Avalon bus. So This driver uses the regmap-spi-avmm for register accessing. Signed-off-by: Xu Yilun <yilun.xu@intel.com> Signed-off-by: Wu Hao <hao.wu@intel.com> Signed-off-by: Matthew Gerlach <matthew.gerlach@linux.intel.com> Signed-off-by: Russ Weight <russell.h.weight@intel.com> Reviewed-by: Tom Rix <trix@redhat.com> Signed-off-by: Lee Jones <lee.jones@linaro.org>
66 lines
1.7 KiB
C
66 lines
1.7 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
|
|
/*
|
|
* Intel MAX 10 Board Management Controller chip.
|
|
*
|
|
* Copyright (C) 2018-2020 Intel Corporation, Inc.
|
|
*/
|
|
#ifndef __MFD_INTEL_M10_BMC_H
|
|
#define __MFD_INTEL_M10_BMC_H
|
|
|
|
#include <linux/regmap.h>
|
|
|
|
#define M10BMC_LEGACY_SYS_BASE 0x300400
|
|
#define M10BMC_SYS_BASE 0x300800
|
|
#define M10BMC_MEM_END 0x200000fc
|
|
|
|
/* Register offset of system registers */
|
|
#define NIOS2_FW_VERSION 0x0
|
|
#define M10BMC_TEST_REG 0x3c
|
|
#define M10BMC_BUILD_VER 0x68
|
|
#define M10BMC_VER_MAJOR_MSK GENMASK(23, 16)
|
|
#define M10BMC_VER_PCB_INFO_MSK GENMASK(31, 24)
|
|
#define M10BMC_VER_LEGACY_INVALID 0xffffffff
|
|
|
|
/**
|
|
* struct intel_m10bmc - Intel MAX 10 BMC parent driver data structure
|
|
* @dev: this device
|
|
* @regmap: the regmap used to access registers by m10bmc itself
|
|
*/
|
|
struct intel_m10bmc {
|
|
struct device *dev;
|
|
struct regmap *regmap;
|
|
};
|
|
|
|
/*
|
|
* register access helper functions.
|
|
*
|
|
* m10bmc_raw_read - read m10bmc register per addr
|
|
* m10bmc_sys_read - read m10bmc system register per offset
|
|
*/
|
|
static inline int
|
|
m10bmc_raw_read(struct intel_m10bmc *m10bmc, unsigned int addr,
|
|
unsigned int *val)
|
|
{
|
|
int ret;
|
|
|
|
ret = regmap_read(m10bmc->regmap, addr, val);
|
|
if (ret)
|
|
dev_err(m10bmc->dev, "fail to read raw reg %x: %d\n",
|
|
addr, ret);
|
|
|
|
return ret;
|
|
}
|
|
|
|
/*
|
|
* The base of the system registers could be configured by HW developers, and
|
|
* in HW SPEC, the base is not added to the addresses of the system registers.
|
|
*
|
|
* This macro helps to simplify the accessing of the system registers. And if
|
|
* the base is reconfigured in HW, SW developers could simply change the
|
|
* M10BMC_SYS_BASE accordingly.
|
|
*/
|
|
#define m10bmc_sys_read(m10bmc, offset, val) \
|
|
m10bmc_raw_read(m10bmc, M10BMC_SYS_BASE + (offset), val)
|
|
|
|
#endif /* __MFD_INTEL_M10_BMC_H */
|