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16f246e69b
For MX50, the HW_ADADIG_DIGPROG register in the ANATOP module will have the correct silicon revision: Major Minor Description 0x50 0x0 TO1.0 0x50 0x1 TO1.1 Signed-off-by: Dinh Nguyen <Dinh.Nguyen@freescale.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
290 lines
9.8 KiB
C
290 lines
9.8 KiB
C
#ifndef __MACH_MX50_H__
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#define __MACH_MX50_H__
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/*
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* IROM
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*/
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#define MX50_IROM_BASE_ADDR 0x0
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#define MX50_IROM_SIZE SZ_64K
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/* TZIC */
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#define MX50_TZIC_BASE_ADDR 0x0fffc000
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#define MX50_TZIC_SIZE SZ_16K
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/*
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* IRAM
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*/
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#define MX50_IRAM_BASE_ADDR 0xf8000000 /* internal ram */
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#define MX50_IRAM_PARTITIONS 16
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#define MX50_IRAM_SIZE (MX50_IRAM_PARTITIONS * SZ_8K) /* 128KB */
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/*
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* Databahn
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*/
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#define MX50_DATABAHN_BASE_ADDR 0x14000000
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/*
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* Graphics Memory of GPU
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*/
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#define MX50_GPU2D_BASE_ADDR 0x20000000
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#define MX50_DEBUG_BASE_ADDR 0x40000000
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#define MX50_DEBUG_SIZE SZ_1M
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#define MX50_ETB_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x00001000)
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#define MX50_ETM_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x00002000)
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#define MX50_TPIU_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x00003000)
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#define MX50_CTI0_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x00004000)
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#define MX50_CTI1_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x00005000)
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#define MX50_CTI2_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x00006000)
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#define MX50_CTI3_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x00007000)
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#define MX50_CORTEX_DBG_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x00008000)
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#define MX50_APBHDMA_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x01000000)
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#define MX50_OCOTP_CTRL_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x01002000)
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#define MX50_DIGCTL_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x01004000)
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#define MX50_GPMI_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x01006000)
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#define MX50_BCH_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x01008000)
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#define MX50_ELCDIF_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x0100a000)
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#define MX50_EPXP_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x0100c000)
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#define MX50_DCP_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x0100e000)
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#define MX50_EPDC_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x01010000)
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#define MX50_QOSC_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x01012000)
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#define MX50_PERFMON_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x01014000)
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#define MX50_SSP_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x01016000)
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#define MX50_ANATOP_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x01018000)
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#define MX50_NIC_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x08000000)
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/*
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* SPBA global module enabled #0
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*/
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#define MX50_SPBA0_BASE_ADDR 0x50000000
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#define MX50_SPBA0_SIZE SZ_1M
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#define MX50_MMC_SDHC1_BASE_ADDR (MX50_SPBA0_BASE_ADDR + 0x00004000)
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#define MX50_MMC_SDHC2_BASE_ADDR (MX50_SPBA0_BASE_ADDR + 0x00008000)
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#define MX50_UART3_BASE_ADDR (MX50_SPBA0_BASE_ADDR + 0x0000c000)
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#define MX50_CSPI1_BASE_ADDR (MX50_SPBA0_BASE_ADDR + 0x00010000)
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#define MX50_SSI2_BASE_ADDR (MX50_SPBA0_BASE_ADDR + 0x00014000)
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#define MX50_MMC_SDHC3_BASE_ADDR (MX50_SPBA0_BASE_ADDR + 0x00020000)
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#define MX50_MMC_SDHC4_BASE_ADDR (MX50_SPBA0_BASE_ADDR + 0x00024000)
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/*
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* AIPS 1
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*/
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#define MX50_AIPS1_BASE_ADDR 0x53f00000
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#define MX50_AIPS1_SIZE SZ_1M
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#define MX50_OTG_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x00080000)
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#define MX50_GPIO1_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x00084000)
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#define MX50_GPIO2_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x00088000)
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#define MX50_GPIO3_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x0008c000)
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#define MX50_GPIO4_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x00090000)
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#define MX50_KPP_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x00094000)
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#define MX50_WDOG_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x00098000)
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#define MX50_GPT1_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000a0000)
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#define MX50_SRTC_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000a4000)
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#define MX50_IOMUXC_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000a8000)
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#define MX50_EPIT1_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000ac000)
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#define MX50_PWM1_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000b4000)
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#define MX50_PWM2_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000b8000)
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#define MX50_UART1_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000bc000)
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#define MX50_UART2_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000c0000)
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#define MX50_SRC_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000d0000)
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#define MX50_CCM_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000d4000)
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#define MX50_GPC_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000d8000)
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#define MX50_GPIO5_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000dc000)
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#define MX50_GPIO6_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000e0000)
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#define MX50_I2C3_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000ec000)
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#define MX50_UART4_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000f0000)
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#define MX50_MSHC_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000f4000)
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#define MX50_RNGB_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000f8000)
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/*
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* AIPS 2
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*/
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#define MX50_AIPS2_BASE_ADDR 0x63f00000
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#define MX50_AIPS2_SIZE SZ_1M
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#define MX50_PLL1_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x00080000)
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#define MX50_PLL2_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x00084000)
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#define MX50_PLL3_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x00088000)
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#define MX50_UART5_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x00090000)
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#define MX50_AHBMAX_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x00094000)
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#define MX50_ARM_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x000a0000)
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#define MX50_OWIRE_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x000a4000)
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#define MX50_CSPI2_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x000ac000)
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#define MX50_SDMA_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x000b0000)
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#define MX50_ROMCP_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x000b8000)
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#define MX50_CSPI3_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x000c0000)
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#define MX50_I2C2_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x000c4000)
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#define MX50_I2C1_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x000c8000)
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#define MX50_SSI1_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x000cc000)
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#define MX50_AUDMUX_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x000d0000)
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#define MX50_WEIM_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x000d8000)
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#define MX50_FEC_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x000ec000)
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/*
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* Memory regions and CS
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*/
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#define MX50_CSD0_BASE_ADDR 0x70000000
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#define MX50_CSD1_BASE_ADDR 0xb0000000
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#define MX50_CS0_BASE_ADDR 0xf0000000
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#define MX50_IO_P2V(x) IMX_IO_P2V(x)
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#define MX50_IO_ADDRESS(x) IOMEM(MX50_IO_P2V(x))
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/*
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* defines for SPBA modules
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*/
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#define MX50_SPBA_SDHC1 0x04
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#define MX50_SPBA_SDHC2 0x08
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#define MX50_SPBA_UART3 0x0c
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#define MX50_SPBA_CSPI1 0x10
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#define MX50_SPBA_SSI2 0x14
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#define MX50_SPBA_SDHC3 0x20
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#define MX50_SPBA_SDHC4 0x24
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#define MX50_SPBA_SPDIF 0x28
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#define MX50_SPBA_ATA 0x30
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#define MX50_SPBA_SLIM 0x34
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#define MX50_SPBA_HSI2C 0x38
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#define MX50_SPBA_CTRL 0x3c
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/*
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* DMA request assignments
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*/
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#define MX50_DMA_REQ_GPC 1
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#define MX50_DMA_REQ_ATA_UART4_RX 2
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#define MX50_DMA_REQ_ATA_UART4_TX 3
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#define MX50_DMA_REQ_CSPI1_RX 6
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#define MX50_DMA_REQ_CSPI1_TX 7
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#define MX50_DMA_REQ_CSPI2_RX 8
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#define MX50_DMA_REQ_CSPI2_TX 9
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#define MX50_DMA_REQ_I2C3_SDHC3 10
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#define MX50_DMA_REQ_SDHC4 11
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#define MX50_DMA_REQ_UART2_FIRI_RX 12
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#define MX50_DMA_REQ_UART2_FIRI_TX 13
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#define MX50_DMA_REQ_EXT0 14
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#define MX50_DMA_REQ_EXT1 15
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#define MX50_DMA_REQ_UART5_RX 16
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#define MX50_DMA_REQ_UART5_TX 17
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#define MX50_DMA_REQ_UART1_RX 18
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#define MX50_DMA_REQ_UART1_TX 19
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#define MX50_DMA_REQ_I2C1_SDHC1 20
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#define MX50_DMA_REQ_I2C2_SDHC2 21
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#define MX50_DMA_REQ_SSI2_RX2 22
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#define MX50_DMA_REQ_SSI2_TX2 23
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#define MX50_DMA_REQ_SSI2_RX1 24
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#define MX50_DMA_REQ_SSI2_TX1 25
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#define MX50_DMA_REQ_SSI1_RX2 26
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#define MX50_DMA_REQ_SSI1_TX2 27
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#define MX50_DMA_REQ_SSI1_RX1 28
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#define MX50_DMA_REQ_SSI1_TX1 29
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#define MX50_DMA_REQ_CSPI_RX 38
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#define MX50_DMA_REQ_CSPI_TX 39
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#define MX50_DMA_REQ_UART3_RX 42
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#define MX50_DMA_REQ_UART3_TX 43
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/*
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* Interrupt numbers
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*/
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#define MX50_INT_MMC_SDHC1 1
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#define MX50_INT_MMC_SDHC2 2
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#define MX50_INT_MMC_SDHC3 3
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#define MX50_INT_MMC_SDHC4 4
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#define MX50_INT_DAP 5
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#define MX50_INT_SDMA 6
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#define MX50_INT_IOMUX 7
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#define MX50_INT_UART4 13
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#define MX50_INT_USB_H1 14
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#define MX50_INT_USB_OTG 18
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#define MX50_INT_DATABAHN 19
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#define MX50_INT_ELCDIF 20
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#define MX50_INT_EPXP 21
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#define MX50_INT_SRTC_NTZ 24
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#define MX50_INT_SRTC_TZ 25
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#define MX50_INT_EPDC 27
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#define MX50_INT_NIC 28
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#define MX50_INT_SSI1 29
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#define MX50_INT_SSI2 30
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#define MX50_INT_UART1 31
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#define MX50_INT_UART2 32
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#define MX50_INT_UART3 33
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#define MX50_INT_RESV34 34
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#define MX50_INT_RESV35 35
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#define MX50_INT_CSPI1 36
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#define MX50_INT_CSPI2 37
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#define MX50_INT_CSPI 38
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#define MX50_INT_GPT 39
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#define MX50_INT_EPIT1 40
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#define MX50_INT_GPIO1_INT7 42
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#define MX50_INT_GPIO1_INT6 43
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#define MX50_INT_GPIO1_INT5 44
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#define MX50_INT_GPIO1_INT4 45
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#define MX50_INT_GPIO1_INT3 46
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#define MX50_INT_GPIO1_INT2 47
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#define MX50_INT_GPIO1_INT1 48
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#define MX50_INT_GPIO1_INT0 49
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#define MX50_INT_GPIO1_LOW 50
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#define MX50_INT_GPIO1_HIGH 51
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#define MX50_INT_GPIO2_LOW 52
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#define MX50_INT_GPIO2_HIGH 53
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#define MX50_INT_GPIO3_LOW 54
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#define MX50_INT_GPIO3_HIGH 55
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#define MX50_INT_GPIO4_LOW 56
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#define MX50_INT_GPIO4_HIGH 57
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#define MX50_INT_WDOG1 58
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#define MX50_INT_KPP 60
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#define MX50_INT_PWM1 61
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#define MX50_INT_I2C1 62
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#define MX50_INT_I2C2 63
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#define MX50_INT_I2C3 64
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#define MX50_INT_RESV65 65
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#define MX50_INT_DCDC 66
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#define MX50_INT_THERMAL_ALARM 67
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#define MX50_INT_ANA3 68
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#define MX50_INT_ANA4 69
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#define MX50_INT_CCM1 71
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#define MX50_INT_CCM2 72
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#define MX50_INT_GPC1 73
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#define MX50_INT_GPC2 74
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#define MX50_INT_SRC 75
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#define MX50_INT_NM 76
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#define MX50_INT_PMU 77
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#define MX50_INT_CTI_IRQ 78
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#define MX50_INT_CTI1_TG0 79
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#define MX50_INT_CTI1_TG1 80
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#define MX50_INT_GPU2_IRQ 84
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#define MX50_INT_GPU2_BUSY 85
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#define MX50_INT_UART5 86
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#define MX50_INT_FEC 87
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#define MX50_INT_OWIRE 88
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#define MX50_INT_CTI1_TG2 89
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#define MX50_INT_SJC 90
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#define MX50_INT_DCP_CHAN1_3 91
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#define MX50_INT_DCP_CHAN0 92
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#define MX50_INT_PWM2 94
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#define MX50_INT_RNGB 97
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#define MX50_INT_CTI1_TG3 98
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#define MX50_INT_RAWNAND_BCH 100
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#define MX50_INT_RAWNAND_GPMI 102
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#define MX50_INT_GPIO5_LOW 103
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#define MX50_INT_GPIO5_HIGH 104
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#define MX50_INT_GPIO6_LOW 105
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#define MX50_INT_GPIO6_HIGH 106
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#define MX50_INT_MSHC 109
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#define MX50_INT_APBHDMA_CHAN0 110
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#define MX50_INT_APBHDMA_CHAN1 111
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#define MX50_INT_APBHDMA_CHAN2 112
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#define MX50_INT_APBHDMA_CHAN3 113
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#define MX50_INT_APBHDMA_CHAN4 114
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#define MX50_INT_APBHDMA_CHAN5 115
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#define MX50_INT_APBHDMA_CHAN6 116
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#define MX50_INT_APBHDMA_CHAN7 117
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#if !defined(__ASSEMBLY__) && !defined(__MXC_BOOT_UNCOMPRESS)
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extern int mx50_revision(void);
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#endif
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#endif /* ifndef __MACH_MX50_H__ */
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