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156d0e290e
PPC64 eBPF JIT compiler. Enable with: echo 1 > /proc/sys/net/core/bpf_jit_enable or echo 2 > /proc/sys/net/core/bpf_jit_enable ... to see the generated JIT code. This can further be processed with tools/net/bpf_jit_disasm. With CONFIG_TEST_BPF=m and 'modprobe test_bpf': test_bpf: Summary: 305 PASSED, 0 FAILED, [297/297 JIT'ed] ... on both ppc64 BE and LE. The details of the approach are documented through various comments in the code. Acked-by: Alexei Starovoitov <ast@kernel.org> Signed-off-by: Naveen N. Rao <naveen.n.rao@linux.vnet.ibm.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
955 lines
27 KiB
C
955 lines
27 KiB
C
/*
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* bpf_jit_comp64.c: eBPF JIT compiler
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*
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* Copyright 2016 Naveen N. Rao <naveen.n.rao@linux.vnet.ibm.com>
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* IBM Corporation
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*
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* Based on the powerpc classic BPF JIT compiler by Matt Evans
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; version 2
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* of the License.
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*/
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#include <linux/moduleloader.h>
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#include <asm/cacheflush.h>
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#include <linux/netdevice.h>
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#include <linux/filter.h>
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#include <linux/if_vlan.h>
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#include <asm/kprobes.h>
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#include "bpf_jit64.h"
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int bpf_jit_enable __read_mostly;
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static void bpf_jit_fill_ill_insns(void *area, unsigned int size)
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{
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int *p = area;
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/* Fill whole space with trap instructions */
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while (p < (int *)((char *)area + size))
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*p++ = BREAKPOINT_INSTRUCTION;
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}
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static inline void bpf_flush_icache(void *start, void *end)
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{
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smp_wmb();
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flush_icache_range((unsigned long)start, (unsigned long)end);
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}
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static inline bool bpf_is_seen_register(struct codegen_context *ctx, int i)
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{
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return (ctx->seen & (1 << (31 - b2p[i])));
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}
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static inline void bpf_set_seen_register(struct codegen_context *ctx, int i)
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{
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ctx->seen |= (1 << (31 - b2p[i]));
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}
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static inline bool bpf_has_stack_frame(struct codegen_context *ctx)
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{
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/*
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* We only need a stack frame if:
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* - we call other functions (kernel helpers), or
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* - the bpf program uses its stack area
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* The latter condition is deduced from the usage of BPF_REG_FP
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*/
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return ctx->seen & SEEN_FUNC || bpf_is_seen_register(ctx, BPF_REG_FP);
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}
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static void bpf_jit_emit_skb_loads(u32 *image, struct codegen_context *ctx)
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{
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/*
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* Load skb->len and skb->data_len
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* r3 points to skb
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*/
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PPC_LWZ(b2p[SKB_HLEN_REG], 3, offsetof(struct sk_buff, len));
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PPC_LWZ(b2p[TMP_REG_1], 3, offsetof(struct sk_buff, data_len));
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/* header_len = len - data_len */
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PPC_SUB(b2p[SKB_HLEN_REG], b2p[SKB_HLEN_REG], b2p[TMP_REG_1]);
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/* skb->data pointer */
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PPC_BPF_LL(b2p[SKB_DATA_REG], 3, offsetof(struct sk_buff, data));
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}
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static void bpf_jit_emit_func_call(u32 *image, struct codegen_context *ctx, u64 func)
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{
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#ifdef PPC64_ELF_ABI_v1
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/* func points to the function descriptor */
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PPC_LI64(b2p[TMP_REG_2], func);
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/* Load actual entry point from function descriptor */
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PPC_BPF_LL(b2p[TMP_REG_1], b2p[TMP_REG_2], 0);
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/* ... and move it to LR */
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PPC_MTLR(b2p[TMP_REG_1]);
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/*
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* Load TOC from function descriptor at offset 8.
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* We can clobber r2 since we get called through a
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* function pointer (so caller will save/restore r2)
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* and since we don't use a TOC ourself.
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*/
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PPC_BPF_LL(2, b2p[TMP_REG_2], 8);
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#else
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/* We can clobber r12 */
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PPC_FUNC_ADDR(12, func);
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PPC_MTLR(12);
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#endif
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PPC_BLRL();
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}
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static void bpf_jit_build_prologue(u32 *image, struct codegen_context *ctx)
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{
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int i;
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bool new_stack_frame = bpf_has_stack_frame(ctx);
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if (new_stack_frame) {
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/*
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* We need a stack frame, but we don't necessarily need to
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* save/restore LR unless we call other functions
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*/
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if (ctx->seen & SEEN_FUNC) {
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EMIT(PPC_INST_MFLR | __PPC_RT(R0));
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PPC_BPF_STL(0, 1, PPC_LR_STKOFF);
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}
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PPC_BPF_STLU(1, 1, -BPF_PPC_STACKFRAME);
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}
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/*
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* Back up non-volatile regs -- BPF registers 6-10
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* If we haven't created our own stack frame, we save these
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* in the protected zone below the previous stack frame
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*/
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for (i = BPF_REG_6; i <= BPF_REG_10; i++)
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if (bpf_is_seen_register(ctx, i))
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PPC_BPF_STL(b2p[i], 1,
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(new_stack_frame ? BPF_PPC_STACKFRAME : 0) -
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(8 * (32 - b2p[i])));
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/*
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* Save additional non-volatile regs if we cache skb
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* Also, setup skb data
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*/
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if (ctx->seen & SEEN_SKB) {
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PPC_BPF_STL(b2p[SKB_HLEN_REG], 1,
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BPF_PPC_STACKFRAME - (8 * (32 - b2p[SKB_HLEN_REG])));
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PPC_BPF_STL(b2p[SKB_DATA_REG], 1,
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BPF_PPC_STACKFRAME - (8 * (32 - b2p[SKB_DATA_REG])));
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bpf_jit_emit_skb_loads(image, ctx);
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}
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/* Setup frame pointer to point to the bpf stack area */
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if (bpf_is_seen_register(ctx, BPF_REG_FP))
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PPC_ADDI(b2p[BPF_REG_FP], 1,
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BPF_PPC_STACKFRAME - BPF_PPC_STACK_SAVE);
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}
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static void bpf_jit_build_epilogue(u32 *image, struct codegen_context *ctx)
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{
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int i;
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bool new_stack_frame = bpf_has_stack_frame(ctx);
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/* Move result to r3 */
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PPC_MR(3, b2p[BPF_REG_0]);
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/* Restore NVRs */
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for (i = BPF_REG_6; i <= BPF_REG_10; i++)
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if (bpf_is_seen_register(ctx, i))
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PPC_BPF_LL(b2p[i], 1,
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(new_stack_frame ? BPF_PPC_STACKFRAME : 0) -
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(8 * (32 - b2p[i])));
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/* Restore non-volatile registers used for skb cache */
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if (ctx->seen & SEEN_SKB) {
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PPC_BPF_LL(b2p[SKB_HLEN_REG], 1,
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BPF_PPC_STACKFRAME - (8 * (32 - b2p[SKB_HLEN_REG])));
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PPC_BPF_LL(b2p[SKB_DATA_REG], 1,
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BPF_PPC_STACKFRAME - (8 * (32 - b2p[SKB_DATA_REG])));
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}
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/* Tear down our stack frame */
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if (new_stack_frame) {
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PPC_ADDI(1, 1, BPF_PPC_STACKFRAME);
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if (ctx->seen & SEEN_FUNC) {
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PPC_BPF_LL(0, 1, PPC_LR_STKOFF);
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PPC_MTLR(0);
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}
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}
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PPC_BLR();
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}
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/* Assemble the body code between the prologue & epilogue */
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static int bpf_jit_build_body(struct bpf_prog *fp, u32 *image,
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struct codegen_context *ctx,
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u32 *addrs)
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{
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const struct bpf_insn *insn = fp->insnsi;
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int flen = fp->len;
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int i;
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/* Start of epilogue code - will only be valid 2nd pass onwards */
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u32 exit_addr = addrs[flen];
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for (i = 0; i < flen; i++) {
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u32 code = insn[i].code;
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u32 dst_reg = b2p[insn[i].dst_reg];
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u32 src_reg = b2p[insn[i].src_reg];
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s16 off = insn[i].off;
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s32 imm = insn[i].imm;
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u64 imm64;
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u8 *func;
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u32 true_cond;
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int stack_local_off;
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/*
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* addrs[] maps a BPF bytecode address into a real offset from
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* the start of the body code.
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*/
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addrs[i] = ctx->idx * 4;
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/*
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* As an optimization, we note down which non-volatile registers
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* are used so that we can only save/restore those in our
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* prologue and epilogue. We do this here regardless of whether
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* the actual BPF instruction uses src/dst registers or not
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* (for instance, BPF_CALL does not use them). The expectation
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* is that those instructions will have src_reg/dst_reg set to
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* 0. Even otherwise, we just lose some prologue/epilogue
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* optimization but everything else should work without
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* any issues.
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*/
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if (dst_reg >= 24 && dst_reg <= 31)
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bpf_set_seen_register(ctx, insn[i].dst_reg);
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if (src_reg >= 24 && src_reg <= 31)
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bpf_set_seen_register(ctx, insn[i].src_reg);
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switch (code) {
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/*
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* Arithmetic operations: ADD/SUB/MUL/DIV/MOD/NEG
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*/
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case BPF_ALU | BPF_ADD | BPF_X: /* (u32) dst += (u32) src */
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case BPF_ALU64 | BPF_ADD | BPF_X: /* dst += src */
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PPC_ADD(dst_reg, dst_reg, src_reg);
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goto bpf_alu32_trunc;
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case BPF_ALU | BPF_SUB | BPF_X: /* (u32) dst -= (u32) src */
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case BPF_ALU64 | BPF_SUB | BPF_X: /* dst -= src */
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PPC_SUB(dst_reg, dst_reg, src_reg);
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goto bpf_alu32_trunc;
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case BPF_ALU | BPF_ADD | BPF_K: /* (u32) dst += (u32) imm */
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case BPF_ALU | BPF_SUB | BPF_K: /* (u32) dst -= (u32) imm */
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case BPF_ALU64 | BPF_ADD | BPF_K: /* dst += imm */
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case BPF_ALU64 | BPF_SUB | BPF_K: /* dst -= imm */
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if (BPF_OP(code) == BPF_SUB)
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imm = -imm;
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if (imm) {
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if (imm >= -32768 && imm < 32768)
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PPC_ADDI(dst_reg, dst_reg, IMM_L(imm));
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else {
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PPC_LI32(b2p[TMP_REG_1], imm);
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PPC_ADD(dst_reg, dst_reg, b2p[TMP_REG_1]);
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}
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}
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goto bpf_alu32_trunc;
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case BPF_ALU | BPF_MUL | BPF_X: /* (u32) dst *= (u32) src */
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case BPF_ALU64 | BPF_MUL | BPF_X: /* dst *= src */
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if (BPF_CLASS(code) == BPF_ALU)
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PPC_MULW(dst_reg, dst_reg, src_reg);
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else
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PPC_MULD(dst_reg, dst_reg, src_reg);
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goto bpf_alu32_trunc;
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case BPF_ALU | BPF_MUL | BPF_K: /* (u32) dst *= (u32) imm */
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case BPF_ALU64 | BPF_MUL | BPF_K: /* dst *= imm */
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if (imm >= -32768 && imm < 32768)
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PPC_MULI(dst_reg, dst_reg, IMM_L(imm));
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else {
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PPC_LI32(b2p[TMP_REG_1], imm);
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if (BPF_CLASS(code) == BPF_ALU)
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PPC_MULW(dst_reg, dst_reg,
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b2p[TMP_REG_1]);
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else
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PPC_MULD(dst_reg, dst_reg,
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b2p[TMP_REG_1]);
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}
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goto bpf_alu32_trunc;
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case BPF_ALU | BPF_DIV | BPF_X: /* (u32) dst /= (u32) src */
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case BPF_ALU | BPF_MOD | BPF_X: /* (u32) dst %= (u32) src */
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PPC_CMPWI(src_reg, 0);
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PPC_BCC_SHORT(COND_NE, (ctx->idx * 4) + 12);
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PPC_LI(b2p[BPF_REG_0], 0);
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PPC_JMP(exit_addr);
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if (BPF_OP(code) == BPF_MOD) {
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PPC_DIVWU(b2p[TMP_REG_1], dst_reg, src_reg);
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PPC_MULW(b2p[TMP_REG_1], src_reg,
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b2p[TMP_REG_1]);
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PPC_SUB(dst_reg, dst_reg, b2p[TMP_REG_1]);
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} else
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PPC_DIVWU(dst_reg, dst_reg, src_reg);
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goto bpf_alu32_trunc;
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case BPF_ALU64 | BPF_DIV | BPF_X: /* dst /= src */
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case BPF_ALU64 | BPF_MOD | BPF_X: /* dst %= src */
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PPC_CMPDI(src_reg, 0);
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PPC_BCC_SHORT(COND_NE, (ctx->idx * 4) + 12);
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PPC_LI(b2p[BPF_REG_0], 0);
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PPC_JMP(exit_addr);
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if (BPF_OP(code) == BPF_MOD) {
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PPC_DIVD(b2p[TMP_REG_1], dst_reg, src_reg);
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PPC_MULD(b2p[TMP_REG_1], src_reg,
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b2p[TMP_REG_1]);
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PPC_SUB(dst_reg, dst_reg, b2p[TMP_REG_1]);
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} else
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PPC_DIVD(dst_reg, dst_reg, src_reg);
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break;
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case BPF_ALU | BPF_MOD | BPF_K: /* (u32) dst %= (u32) imm */
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case BPF_ALU | BPF_DIV | BPF_K: /* (u32) dst /= (u32) imm */
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case BPF_ALU64 | BPF_MOD | BPF_K: /* dst %= imm */
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case BPF_ALU64 | BPF_DIV | BPF_K: /* dst /= imm */
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if (imm == 0)
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return -EINVAL;
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else if (imm == 1)
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goto bpf_alu32_trunc;
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PPC_LI32(b2p[TMP_REG_1], imm);
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switch (BPF_CLASS(code)) {
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case BPF_ALU:
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if (BPF_OP(code) == BPF_MOD) {
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PPC_DIVWU(b2p[TMP_REG_2], dst_reg,
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b2p[TMP_REG_1]);
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PPC_MULW(b2p[TMP_REG_1],
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b2p[TMP_REG_1],
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b2p[TMP_REG_2]);
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PPC_SUB(dst_reg, dst_reg,
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b2p[TMP_REG_1]);
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} else
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PPC_DIVWU(dst_reg, dst_reg,
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b2p[TMP_REG_1]);
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break;
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case BPF_ALU64:
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if (BPF_OP(code) == BPF_MOD) {
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PPC_DIVD(b2p[TMP_REG_2], dst_reg,
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b2p[TMP_REG_1]);
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PPC_MULD(b2p[TMP_REG_1],
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b2p[TMP_REG_1],
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b2p[TMP_REG_2]);
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PPC_SUB(dst_reg, dst_reg,
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b2p[TMP_REG_1]);
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} else
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PPC_DIVD(dst_reg, dst_reg,
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b2p[TMP_REG_1]);
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break;
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}
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goto bpf_alu32_trunc;
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case BPF_ALU | BPF_NEG: /* (u32) dst = -dst */
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case BPF_ALU64 | BPF_NEG: /* dst = -dst */
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PPC_NEG(dst_reg, dst_reg);
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goto bpf_alu32_trunc;
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/*
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* Logical operations: AND/OR/XOR/[A]LSH/[A]RSH
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*/
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case BPF_ALU | BPF_AND | BPF_X: /* (u32) dst = dst & src */
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case BPF_ALU64 | BPF_AND | BPF_X: /* dst = dst & src */
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PPC_AND(dst_reg, dst_reg, src_reg);
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goto bpf_alu32_trunc;
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case BPF_ALU | BPF_AND | BPF_K: /* (u32) dst = dst & imm */
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case BPF_ALU64 | BPF_AND | BPF_K: /* dst = dst & imm */
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if (!IMM_H(imm))
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PPC_ANDI(dst_reg, dst_reg, IMM_L(imm));
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else {
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/* Sign-extended */
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PPC_LI32(b2p[TMP_REG_1], imm);
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PPC_AND(dst_reg, dst_reg, b2p[TMP_REG_1]);
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}
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goto bpf_alu32_trunc;
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case BPF_ALU | BPF_OR | BPF_X: /* dst = (u32) dst | (u32) src */
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case BPF_ALU64 | BPF_OR | BPF_X: /* dst = dst | src */
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PPC_OR(dst_reg, dst_reg, src_reg);
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goto bpf_alu32_trunc;
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case BPF_ALU | BPF_OR | BPF_K:/* dst = (u32) dst | (u32) imm */
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case BPF_ALU64 | BPF_OR | BPF_K:/* dst = dst | imm */
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if (imm < 0 && BPF_CLASS(code) == BPF_ALU64) {
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/* Sign-extended */
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PPC_LI32(b2p[TMP_REG_1], imm);
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PPC_OR(dst_reg, dst_reg, b2p[TMP_REG_1]);
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} else {
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if (IMM_L(imm))
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PPC_ORI(dst_reg, dst_reg, IMM_L(imm));
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if (IMM_H(imm))
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PPC_ORIS(dst_reg, dst_reg, IMM_H(imm));
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}
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goto bpf_alu32_trunc;
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case BPF_ALU | BPF_XOR | BPF_X: /* (u32) dst ^= src */
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case BPF_ALU64 | BPF_XOR | BPF_X: /* dst ^= src */
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PPC_XOR(dst_reg, dst_reg, src_reg);
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goto bpf_alu32_trunc;
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case BPF_ALU | BPF_XOR | BPF_K: /* (u32) dst ^= (u32) imm */
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case BPF_ALU64 | BPF_XOR | BPF_K: /* dst ^= imm */
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if (imm < 0 && BPF_CLASS(code) == BPF_ALU64) {
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/* Sign-extended */
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PPC_LI32(b2p[TMP_REG_1], imm);
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PPC_XOR(dst_reg, dst_reg, b2p[TMP_REG_1]);
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} else {
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if (IMM_L(imm))
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PPC_XORI(dst_reg, dst_reg, IMM_L(imm));
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if (IMM_H(imm))
|
|
PPC_XORIS(dst_reg, dst_reg, IMM_H(imm));
|
|
}
|
|
goto bpf_alu32_trunc;
|
|
case BPF_ALU | BPF_LSH | BPF_X: /* (u32) dst <<= (u32) src */
|
|
/* slw clears top 32 bits */
|
|
PPC_SLW(dst_reg, dst_reg, src_reg);
|
|
break;
|
|
case BPF_ALU64 | BPF_LSH | BPF_X: /* dst <<= src; */
|
|
PPC_SLD(dst_reg, dst_reg, src_reg);
|
|
break;
|
|
case BPF_ALU | BPF_LSH | BPF_K: /* (u32) dst <<== (u32) imm */
|
|
/* with imm 0, we still need to clear top 32 bits */
|
|
PPC_SLWI(dst_reg, dst_reg, imm);
|
|
break;
|
|
case BPF_ALU64 | BPF_LSH | BPF_K: /* dst <<== imm */
|
|
if (imm != 0)
|
|
PPC_SLDI(dst_reg, dst_reg, imm);
|
|
break;
|
|
case BPF_ALU | BPF_RSH | BPF_X: /* (u32) dst >>= (u32) src */
|
|
PPC_SRW(dst_reg, dst_reg, src_reg);
|
|
break;
|
|
case BPF_ALU64 | BPF_RSH | BPF_X: /* dst >>= src */
|
|
PPC_SRD(dst_reg, dst_reg, src_reg);
|
|
break;
|
|
case BPF_ALU | BPF_RSH | BPF_K: /* (u32) dst >>= (u32) imm */
|
|
PPC_SRWI(dst_reg, dst_reg, imm);
|
|
break;
|
|
case BPF_ALU64 | BPF_RSH | BPF_K: /* dst >>= imm */
|
|
if (imm != 0)
|
|
PPC_SRDI(dst_reg, dst_reg, imm);
|
|
break;
|
|
case BPF_ALU64 | BPF_ARSH | BPF_X: /* (s64) dst >>= src */
|
|
PPC_SRAD(dst_reg, dst_reg, src_reg);
|
|
break;
|
|
case BPF_ALU64 | BPF_ARSH | BPF_K: /* (s64) dst >>= imm */
|
|
if (imm != 0)
|
|
PPC_SRADI(dst_reg, dst_reg, imm);
|
|
break;
|
|
|
|
/*
|
|
* MOV
|
|
*/
|
|
case BPF_ALU | BPF_MOV | BPF_X: /* (u32) dst = src */
|
|
case BPF_ALU64 | BPF_MOV | BPF_X: /* dst = src */
|
|
PPC_MR(dst_reg, src_reg);
|
|
goto bpf_alu32_trunc;
|
|
case BPF_ALU | BPF_MOV | BPF_K: /* (u32) dst = imm */
|
|
case BPF_ALU64 | BPF_MOV | BPF_K: /* dst = (s64) imm */
|
|
PPC_LI32(dst_reg, imm);
|
|
if (imm < 0)
|
|
goto bpf_alu32_trunc;
|
|
break;
|
|
|
|
bpf_alu32_trunc:
|
|
/* Truncate to 32-bits */
|
|
if (BPF_CLASS(code) == BPF_ALU)
|
|
PPC_RLWINM(dst_reg, dst_reg, 0, 0, 31);
|
|
break;
|
|
|
|
/*
|
|
* BPF_FROM_BE/LE
|
|
*/
|
|
case BPF_ALU | BPF_END | BPF_FROM_LE:
|
|
case BPF_ALU | BPF_END | BPF_FROM_BE:
|
|
#ifdef __BIG_ENDIAN__
|
|
if (BPF_SRC(code) == BPF_FROM_BE)
|
|
goto emit_clear;
|
|
#else /* !__BIG_ENDIAN__ */
|
|
if (BPF_SRC(code) == BPF_FROM_LE)
|
|
goto emit_clear;
|
|
#endif
|
|
switch (imm) {
|
|
case 16:
|
|
/* Rotate 8 bits left & mask with 0x0000ff00 */
|
|
PPC_RLWINM(b2p[TMP_REG_1], dst_reg, 8, 16, 23);
|
|
/* Rotate 8 bits right & insert LSB to reg */
|
|
PPC_RLWIMI(b2p[TMP_REG_1], dst_reg, 24, 24, 31);
|
|
/* Move result back to dst_reg */
|
|
PPC_MR(dst_reg, b2p[TMP_REG_1]);
|
|
break;
|
|
case 32:
|
|
/*
|
|
* Rotate word left by 8 bits:
|
|
* 2 bytes are already in their final position
|
|
* -- byte 2 and 4 (of bytes 1, 2, 3 and 4)
|
|
*/
|
|
PPC_RLWINM(b2p[TMP_REG_1], dst_reg, 8, 0, 31);
|
|
/* Rotate 24 bits and insert byte 1 */
|
|
PPC_RLWIMI(b2p[TMP_REG_1], dst_reg, 24, 0, 7);
|
|
/* Rotate 24 bits and insert byte 3 */
|
|
PPC_RLWIMI(b2p[TMP_REG_1], dst_reg, 24, 16, 23);
|
|
PPC_MR(dst_reg, b2p[TMP_REG_1]);
|
|
break;
|
|
case 64:
|
|
/*
|
|
* Way easier and faster(?) to store the value
|
|
* into stack and then use ldbrx
|
|
*
|
|
* First, determine where in stack we can store
|
|
* this:
|
|
* - if we have allotted a stack frame, then we
|
|
* will utilize the area set aside by
|
|
* BPF_PPC_STACK_LOCALS
|
|
* - else, we use the area beneath the NV GPR
|
|
* save area
|
|
*
|
|
* ctx->seen will be reliable in pass2, but
|
|
* the instructions generated will remain the
|
|
* same across all passes
|
|
*/
|
|
if (bpf_has_stack_frame(ctx))
|
|
stack_local_off = STACK_FRAME_MIN_SIZE;
|
|
else
|
|
stack_local_off = -(BPF_PPC_STACK_SAVE + 8);
|
|
|
|
PPC_STD(dst_reg, 1, stack_local_off);
|
|
PPC_ADDI(b2p[TMP_REG_1], 1, stack_local_off);
|
|
PPC_LDBRX(dst_reg, 0, b2p[TMP_REG_1]);
|
|
break;
|
|
}
|
|
break;
|
|
|
|
emit_clear:
|
|
switch (imm) {
|
|
case 16:
|
|
/* zero-extend 16 bits into 64 bits */
|
|
PPC_RLDICL(dst_reg, dst_reg, 0, 48);
|
|
break;
|
|
case 32:
|
|
/* zero-extend 32 bits into 64 bits */
|
|
PPC_RLDICL(dst_reg, dst_reg, 0, 32);
|
|
break;
|
|
case 64:
|
|
/* nop */
|
|
break;
|
|
}
|
|
break;
|
|
|
|
/*
|
|
* BPF_ST(X)
|
|
*/
|
|
case BPF_STX | BPF_MEM | BPF_B: /* *(u8 *)(dst + off) = src */
|
|
case BPF_ST | BPF_MEM | BPF_B: /* *(u8 *)(dst + off) = imm */
|
|
if (BPF_CLASS(code) == BPF_ST) {
|
|
PPC_LI(b2p[TMP_REG_1], imm);
|
|
src_reg = b2p[TMP_REG_1];
|
|
}
|
|
PPC_STB(src_reg, dst_reg, off);
|
|
break;
|
|
case BPF_STX | BPF_MEM | BPF_H: /* (u16 *)(dst + off) = src */
|
|
case BPF_ST | BPF_MEM | BPF_H: /* (u16 *)(dst + off) = imm */
|
|
if (BPF_CLASS(code) == BPF_ST) {
|
|
PPC_LI(b2p[TMP_REG_1], imm);
|
|
src_reg = b2p[TMP_REG_1];
|
|
}
|
|
PPC_STH(src_reg, dst_reg, off);
|
|
break;
|
|
case BPF_STX | BPF_MEM | BPF_W: /* *(u32 *)(dst + off) = src */
|
|
case BPF_ST | BPF_MEM | BPF_W: /* *(u32 *)(dst + off) = imm */
|
|
if (BPF_CLASS(code) == BPF_ST) {
|
|
PPC_LI32(b2p[TMP_REG_1], imm);
|
|
src_reg = b2p[TMP_REG_1];
|
|
}
|
|
PPC_STW(src_reg, dst_reg, off);
|
|
break;
|
|
case BPF_STX | BPF_MEM | BPF_DW: /* (u64 *)(dst + off) = src */
|
|
case BPF_ST | BPF_MEM | BPF_DW: /* *(u64 *)(dst + off) = imm */
|
|
if (BPF_CLASS(code) == BPF_ST) {
|
|
PPC_LI32(b2p[TMP_REG_1], imm);
|
|
src_reg = b2p[TMP_REG_1];
|
|
}
|
|
PPC_STD(src_reg, dst_reg, off);
|
|
break;
|
|
|
|
/*
|
|
* BPF_STX XADD (atomic_add)
|
|
*/
|
|
/* *(u32 *)(dst + off) += src */
|
|
case BPF_STX | BPF_XADD | BPF_W:
|
|
/* Get EA into TMP_REG_1 */
|
|
PPC_ADDI(b2p[TMP_REG_1], dst_reg, off);
|
|
/* error if EA is not word-aligned */
|
|
PPC_ANDI(b2p[TMP_REG_2], b2p[TMP_REG_1], 0x03);
|
|
PPC_BCC_SHORT(COND_EQ, (ctx->idx * 4) + 12);
|
|
PPC_LI(b2p[BPF_REG_0], 0);
|
|
PPC_JMP(exit_addr);
|
|
/* load value from memory into TMP_REG_2 */
|
|
PPC_BPF_LWARX(b2p[TMP_REG_2], 0, b2p[TMP_REG_1], 0);
|
|
/* add value from src_reg into this */
|
|
PPC_ADD(b2p[TMP_REG_2], b2p[TMP_REG_2], src_reg);
|
|
/* store result back */
|
|
PPC_BPF_STWCX(b2p[TMP_REG_2], 0, b2p[TMP_REG_1]);
|
|
/* we're done if this succeeded */
|
|
PPC_BCC_SHORT(COND_EQ, (ctx->idx * 4) + (7*4));
|
|
/* otherwise, let's try once more */
|
|
PPC_BPF_LWARX(b2p[TMP_REG_2], 0, b2p[TMP_REG_1], 0);
|
|
PPC_ADD(b2p[TMP_REG_2], b2p[TMP_REG_2], src_reg);
|
|
PPC_BPF_STWCX(b2p[TMP_REG_2], 0, b2p[TMP_REG_1]);
|
|
/* exit if the store was not successful */
|
|
PPC_LI(b2p[BPF_REG_0], 0);
|
|
PPC_BCC(COND_NE, exit_addr);
|
|
break;
|
|
/* *(u64 *)(dst + off) += src */
|
|
case BPF_STX | BPF_XADD | BPF_DW:
|
|
PPC_ADDI(b2p[TMP_REG_1], dst_reg, off);
|
|
/* error if EA is not doubleword-aligned */
|
|
PPC_ANDI(b2p[TMP_REG_2], b2p[TMP_REG_1], 0x07);
|
|
PPC_BCC_SHORT(COND_EQ, (ctx->idx * 4) + (3*4));
|
|
PPC_LI(b2p[BPF_REG_0], 0);
|
|
PPC_JMP(exit_addr);
|
|
PPC_BPF_LDARX(b2p[TMP_REG_2], 0, b2p[TMP_REG_1], 0);
|
|
PPC_ADD(b2p[TMP_REG_2], b2p[TMP_REG_2], src_reg);
|
|
PPC_BPF_STDCX(b2p[TMP_REG_2], 0, b2p[TMP_REG_1]);
|
|
PPC_BCC_SHORT(COND_EQ, (ctx->idx * 4) + (7*4));
|
|
PPC_BPF_LDARX(b2p[TMP_REG_2], 0, b2p[TMP_REG_1], 0);
|
|
PPC_ADD(b2p[TMP_REG_2], b2p[TMP_REG_2], src_reg);
|
|
PPC_BPF_STDCX(b2p[TMP_REG_2], 0, b2p[TMP_REG_1]);
|
|
PPC_LI(b2p[BPF_REG_0], 0);
|
|
PPC_BCC(COND_NE, exit_addr);
|
|
break;
|
|
|
|
/*
|
|
* BPF_LDX
|
|
*/
|
|
/* dst = *(u8 *)(ul) (src + off) */
|
|
case BPF_LDX | BPF_MEM | BPF_B:
|
|
PPC_LBZ(dst_reg, src_reg, off);
|
|
break;
|
|
/* dst = *(u16 *)(ul) (src + off) */
|
|
case BPF_LDX | BPF_MEM | BPF_H:
|
|
PPC_LHZ(dst_reg, src_reg, off);
|
|
break;
|
|
/* dst = *(u32 *)(ul) (src + off) */
|
|
case BPF_LDX | BPF_MEM | BPF_W:
|
|
PPC_LWZ(dst_reg, src_reg, off);
|
|
break;
|
|
/* dst = *(u64 *)(ul) (src + off) */
|
|
case BPF_LDX | BPF_MEM | BPF_DW:
|
|
PPC_LD(dst_reg, src_reg, off);
|
|
break;
|
|
|
|
/*
|
|
* Doubleword load
|
|
* 16 byte instruction that uses two 'struct bpf_insn'
|
|
*/
|
|
case BPF_LD | BPF_IMM | BPF_DW: /* dst = (u64) imm */
|
|
imm64 = ((u64)(u32) insn[i].imm) |
|
|
(((u64)(u32) insn[i+1].imm) << 32);
|
|
/* Adjust for two bpf instructions */
|
|
addrs[++i] = ctx->idx * 4;
|
|
PPC_LI64(dst_reg, imm64);
|
|
break;
|
|
|
|
/*
|
|
* Return/Exit
|
|
*/
|
|
case BPF_JMP | BPF_EXIT:
|
|
/*
|
|
* If this isn't the very last instruction, branch to
|
|
* the epilogue. If we _are_ the last instruction,
|
|
* we'll just fall through to the epilogue.
|
|
*/
|
|
if (i != flen - 1)
|
|
PPC_JMP(exit_addr);
|
|
/* else fall through to the epilogue */
|
|
break;
|
|
|
|
/*
|
|
* Call kernel helper
|
|
*/
|
|
case BPF_JMP | BPF_CALL:
|
|
ctx->seen |= SEEN_FUNC;
|
|
func = (u8 *) __bpf_call_base + imm;
|
|
|
|
/* Save skb pointer if we need to re-cache skb data */
|
|
if (bpf_helper_changes_skb_data(func))
|
|
PPC_BPF_STL(3, 1, STACK_FRAME_MIN_SIZE);
|
|
|
|
bpf_jit_emit_func_call(image, ctx, (u64)func);
|
|
|
|
/* move return value from r3 to BPF_REG_0 */
|
|
PPC_MR(b2p[BPF_REG_0], 3);
|
|
|
|
/* refresh skb cache */
|
|
if (bpf_helper_changes_skb_data(func)) {
|
|
/* reload skb pointer to r3 */
|
|
PPC_BPF_LL(3, 1, STACK_FRAME_MIN_SIZE);
|
|
bpf_jit_emit_skb_loads(image, ctx);
|
|
}
|
|
break;
|
|
|
|
/*
|
|
* Jumps and branches
|
|
*/
|
|
case BPF_JMP | BPF_JA:
|
|
PPC_JMP(addrs[i + 1 + off]);
|
|
break;
|
|
|
|
case BPF_JMP | BPF_JGT | BPF_K:
|
|
case BPF_JMP | BPF_JGT | BPF_X:
|
|
case BPF_JMP | BPF_JSGT | BPF_K:
|
|
case BPF_JMP | BPF_JSGT | BPF_X:
|
|
true_cond = COND_GT;
|
|
goto cond_branch;
|
|
case BPF_JMP | BPF_JGE | BPF_K:
|
|
case BPF_JMP | BPF_JGE | BPF_X:
|
|
case BPF_JMP | BPF_JSGE | BPF_K:
|
|
case BPF_JMP | BPF_JSGE | BPF_X:
|
|
true_cond = COND_GE;
|
|
goto cond_branch;
|
|
case BPF_JMP | BPF_JEQ | BPF_K:
|
|
case BPF_JMP | BPF_JEQ | BPF_X:
|
|
true_cond = COND_EQ;
|
|
goto cond_branch;
|
|
case BPF_JMP | BPF_JNE | BPF_K:
|
|
case BPF_JMP | BPF_JNE | BPF_X:
|
|
true_cond = COND_NE;
|
|
goto cond_branch;
|
|
case BPF_JMP | BPF_JSET | BPF_K:
|
|
case BPF_JMP | BPF_JSET | BPF_X:
|
|
true_cond = COND_NE;
|
|
/* Fall through */
|
|
|
|
cond_branch:
|
|
switch (code) {
|
|
case BPF_JMP | BPF_JGT | BPF_X:
|
|
case BPF_JMP | BPF_JGE | BPF_X:
|
|
case BPF_JMP | BPF_JEQ | BPF_X:
|
|
case BPF_JMP | BPF_JNE | BPF_X:
|
|
/* unsigned comparison */
|
|
PPC_CMPLD(dst_reg, src_reg);
|
|
break;
|
|
case BPF_JMP | BPF_JSGT | BPF_X:
|
|
case BPF_JMP | BPF_JSGE | BPF_X:
|
|
/* signed comparison */
|
|
PPC_CMPD(dst_reg, src_reg);
|
|
break;
|
|
case BPF_JMP | BPF_JSET | BPF_X:
|
|
PPC_AND_DOT(b2p[TMP_REG_1], dst_reg, src_reg);
|
|
break;
|
|
case BPF_JMP | BPF_JNE | BPF_K:
|
|
case BPF_JMP | BPF_JEQ | BPF_K:
|
|
case BPF_JMP | BPF_JGT | BPF_K:
|
|
case BPF_JMP | BPF_JGE | BPF_K:
|
|
/*
|
|
* Need sign-extended load, so only positive
|
|
* values can be used as imm in cmpldi
|
|
*/
|
|
if (imm >= 0 && imm < 32768)
|
|
PPC_CMPLDI(dst_reg, imm);
|
|
else {
|
|
/* sign-extending load */
|
|
PPC_LI32(b2p[TMP_REG_1], imm);
|
|
/* ... but unsigned comparison */
|
|
PPC_CMPLD(dst_reg, b2p[TMP_REG_1]);
|
|
}
|
|
break;
|
|
case BPF_JMP | BPF_JSGT | BPF_K:
|
|
case BPF_JMP | BPF_JSGE | BPF_K:
|
|
/*
|
|
* signed comparison, so any 16-bit value
|
|
* can be used in cmpdi
|
|
*/
|
|
if (imm >= -32768 && imm < 32768)
|
|
PPC_CMPDI(dst_reg, imm);
|
|
else {
|
|
PPC_LI32(b2p[TMP_REG_1], imm);
|
|
PPC_CMPD(dst_reg, b2p[TMP_REG_1]);
|
|
}
|
|
break;
|
|
case BPF_JMP | BPF_JSET | BPF_K:
|
|
/* andi does not sign-extend the immediate */
|
|
if (imm >= 0 && imm < 32768)
|
|
/* PPC_ANDI is _only/always_ dot-form */
|
|
PPC_ANDI(b2p[TMP_REG_1], dst_reg, imm);
|
|
else {
|
|
PPC_LI32(b2p[TMP_REG_1], imm);
|
|
PPC_AND_DOT(b2p[TMP_REG_1], dst_reg,
|
|
b2p[TMP_REG_1]);
|
|
}
|
|
break;
|
|
}
|
|
PPC_BCC(true_cond, addrs[i + 1 + off]);
|
|
break;
|
|
|
|
/*
|
|
* Loads from packet header/data
|
|
* Assume 32-bit input value in imm and X (src_reg)
|
|
*/
|
|
|
|
/* Absolute loads */
|
|
case BPF_LD | BPF_W | BPF_ABS:
|
|
func = (u8 *)CHOOSE_LOAD_FUNC(imm, sk_load_word);
|
|
goto common_load_abs;
|
|
case BPF_LD | BPF_H | BPF_ABS:
|
|
func = (u8 *)CHOOSE_LOAD_FUNC(imm, sk_load_half);
|
|
goto common_load_abs;
|
|
case BPF_LD | BPF_B | BPF_ABS:
|
|
func = (u8 *)CHOOSE_LOAD_FUNC(imm, sk_load_byte);
|
|
common_load_abs:
|
|
/*
|
|
* Load from [imm]
|
|
* Load into r4, which can just be passed onto
|
|
* skb load helpers as the second parameter
|
|
*/
|
|
PPC_LI32(4, imm);
|
|
goto common_load;
|
|
|
|
/* Indirect loads */
|
|
case BPF_LD | BPF_W | BPF_IND:
|
|
func = (u8 *)sk_load_word;
|
|
goto common_load_ind;
|
|
case BPF_LD | BPF_H | BPF_IND:
|
|
func = (u8 *)sk_load_half;
|
|
goto common_load_ind;
|
|
case BPF_LD | BPF_B | BPF_IND:
|
|
func = (u8 *)sk_load_byte;
|
|
common_load_ind:
|
|
/*
|
|
* Load from [src_reg + imm]
|
|
* Treat src_reg as a 32-bit value
|
|
*/
|
|
PPC_EXTSW(4, src_reg);
|
|
if (imm) {
|
|
if (imm >= -32768 && imm < 32768)
|
|
PPC_ADDI(4, 4, IMM_L(imm));
|
|
else {
|
|
PPC_LI32(b2p[TMP_REG_1], imm);
|
|
PPC_ADD(4, 4, b2p[TMP_REG_1]);
|
|
}
|
|
}
|
|
|
|
common_load:
|
|
ctx->seen |= SEEN_SKB;
|
|
ctx->seen |= SEEN_FUNC;
|
|
bpf_jit_emit_func_call(image, ctx, (u64)func);
|
|
|
|
/*
|
|
* Helper returns 'lt' condition on error, and an
|
|
* appropriate return value in BPF_REG_0
|
|
*/
|
|
PPC_BCC(COND_LT, exit_addr);
|
|
break;
|
|
|
|
/*
|
|
* TODO: Tail call
|
|
*/
|
|
case BPF_JMP | BPF_CALL | BPF_X:
|
|
|
|
default:
|
|
/*
|
|
* The filter contains something cruel & unusual.
|
|
* We don't handle it, but also there shouldn't be
|
|
* anything missing from our list.
|
|
*/
|
|
pr_err_ratelimited("eBPF filter opcode %04x (@%d) unsupported\n",
|
|
code, i);
|
|
return -ENOTSUPP;
|
|
}
|
|
}
|
|
|
|
/* Set end-of-body-code address for exit. */
|
|
addrs[i] = ctx->idx * 4;
|
|
|
|
return 0;
|
|
}
|
|
|
|
void bpf_jit_compile(struct bpf_prog *fp) { }
|
|
|
|
struct bpf_prog *bpf_int_jit_compile(struct bpf_prog *fp)
|
|
{
|
|
u32 proglen;
|
|
u32 alloclen;
|
|
u8 *image = NULL;
|
|
u32 *code_base;
|
|
u32 *addrs;
|
|
struct codegen_context cgctx;
|
|
int pass;
|
|
int flen;
|
|
struct bpf_binary_header *bpf_hdr;
|
|
|
|
if (!bpf_jit_enable)
|
|
return fp;
|
|
|
|
flen = fp->len;
|
|
addrs = kzalloc((flen+1) * sizeof(*addrs), GFP_KERNEL);
|
|
if (addrs == NULL)
|
|
return fp;
|
|
|
|
cgctx.idx = 0;
|
|
cgctx.seen = 0;
|
|
/* Scouting faux-generate pass 0 */
|
|
if (bpf_jit_build_body(fp, 0, &cgctx, addrs))
|
|
/* We hit something illegal or unsupported. */
|
|
goto out;
|
|
|
|
/*
|
|
* Pretend to build prologue, given the features we've seen. This will
|
|
* update ctgtx.idx as it pretends to output instructions, then we can
|
|
* calculate total size from idx.
|
|
*/
|
|
bpf_jit_build_prologue(0, &cgctx);
|
|
bpf_jit_build_epilogue(0, &cgctx);
|
|
|
|
proglen = cgctx.idx * 4;
|
|
alloclen = proglen + FUNCTION_DESCR_SIZE;
|
|
|
|
bpf_hdr = bpf_jit_binary_alloc(alloclen, &image, 4,
|
|
bpf_jit_fill_ill_insns);
|
|
if (!bpf_hdr)
|
|
goto out;
|
|
|
|
code_base = (u32 *)(image + FUNCTION_DESCR_SIZE);
|
|
|
|
/* Code generation passes 1-2 */
|
|
for (pass = 1; pass < 3; pass++) {
|
|
/* Now build the prologue, body code & epilogue for real. */
|
|
cgctx.idx = 0;
|
|
bpf_jit_build_prologue(code_base, &cgctx);
|
|
bpf_jit_build_body(fp, code_base, &cgctx, addrs);
|
|
bpf_jit_build_epilogue(code_base, &cgctx);
|
|
|
|
if (bpf_jit_enable > 1)
|
|
pr_info("Pass %d: shrink = %d, seen = 0x%x\n", pass,
|
|
proglen - (cgctx.idx * 4), cgctx.seen);
|
|
}
|
|
|
|
if (bpf_jit_enable > 1)
|
|
/*
|
|
* Note that we output the base address of the code_base
|
|
* rather than image, since opcodes are in code_base.
|
|
*/
|
|
bpf_jit_dump(flen, proglen, pass, code_base);
|
|
|
|
if (image) {
|
|
bpf_flush_icache(bpf_hdr, image + alloclen);
|
|
#ifdef PPC64_ELF_ABI_v1
|
|
/* Function descriptor nastiness: Address + TOC */
|
|
((u64 *)image)[0] = (u64)code_base;
|
|
((u64 *)image)[1] = local_paca->kernel_toc;
|
|
#endif
|
|
fp->bpf_func = (void *)image;
|
|
fp->jited = 1;
|
|
}
|
|
|
|
out:
|
|
kfree(addrs);
|
|
return fp;
|
|
}
|
|
|
|
void bpf_jit_free(struct bpf_prog *fp)
|
|
{
|
|
unsigned long addr = (unsigned long)fp->bpf_func & PAGE_MASK;
|
|
struct bpf_binary_header *bpf_hdr = (void *)addr;
|
|
|
|
if (fp->jited)
|
|
bpf_jit_binary_free(bpf_hdr);
|
|
|
|
bpf_prog_unlock_free(fp);
|
|
}
|