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9d12ba86f8
Add Broadcom Secure Processing Unit (SPU) crypto driver for SPU hardware crypto offload. The driver supports ablkcipher, ahash, and aead symmetric crypto operations. Signed-off-by: Steve Lin <steven.lin1@broadcom.com> Signed-off-by: Rob Rice <rob.rice@broadcom.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
229 lines
8.3 KiB
C
229 lines
8.3 KiB
C
/*
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* Copyright 2016 Broadcom
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License, version 2, as
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* published by the Free Software Foundation (the "GPL").
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License version 2 (GPLv2) for more details.
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*
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* You should have received a copy of the GNU General Public License
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* version 2 (GPLv2) along with this source code.
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*/
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/*
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* This file contains SPU message definitions specific to SPU2.
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*/
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#ifndef _SPU2_H
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#define _SPU2_H
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enum spu2_cipher_type {
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SPU2_CIPHER_TYPE_NONE = 0x0,
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SPU2_CIPHER_TYPE_AES128 = 0x1,
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SPU2_CIPHER_TYPE_AES192 = 0x2,
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SPU2_CIPHER_TYPE_AES256 = 0x3,
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SPU2_CIPHER_TYPE_DES = 0x4,
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SPU2_CIPHER_TYPE_3DES = 0x5,
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SPU2_CIPHER_TYPE_LAST
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};
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enum spu2_cipher_mode {
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SPU2_CIPHER_MODE_ECB = 0x0,
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SPU2_CIPHER_MODE_CBC = 0x1,
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SPU2_CIPHER_MODE_CTR = 0x2,
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SPU2_CIPHER_MODE_CFB = 0x3,
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SPU2_CIPHER_MODE_OFB = 0x4,
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SPU2_CIPHER_MODE_XTS = 0x5,
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SPU2_CIPHER_MODE_CCM = 0x6,
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SPU2_CIPHER_MODE_GCM = 0x7,
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SPU2_CIPHER_MODE_LAST
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};
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enum spu2_hash_type {
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SPU2_HASH_TYPE_NONE = 0x0,
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SPU2_HASH_TYPE_AES128 = 0x1,
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SPU2_HASH_TYPE_AES192 = 0x2,
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SPU2_HASH_TYPE_AES256 = 0x3,
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SPU2_HASH_TYPE_MD5 = 0x6,
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SPU2_HASH_TYPE_SHA1 = 0x7,
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SPU2_HASH_TYPE_SHA224 = 0x8,
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SPU2_HASH_TYPE_SHA256 = 0x9,
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SPU2_HASH_TYPE_SHA384 = 0xa,
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SPU2_HASH_TYPE_SHA512 = 0xb,
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SPU2_HASH_TYPE_SHA512_224 = 0xc,
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SPU2_HASH_TYPE_SHA512_256 = 0xd,
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SPU2_HASH_TYPE_SHA3_224 = 0xe,
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SPU2_HASH_TYPE_SHA3_256 = 0xf,
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SPU2_HASH_TYPE_SHA3_384 = 0x10,
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SPU2_HASH_TYPE_SHA3_512 = 0x11,
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SPU2_HASH_TYPE_LAST
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};
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enum spu2_hash_mode {
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SPU2_HASH_MODE_CMAC = 0x0,
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SPU2_HASH_MODE_CBC_MAC = 0x1,
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SPU2_HASH_MODE_XCBC_MAC = 0x2,
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SPU2_HASH_MODE_HMAC = 0x3,
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SPU2_HASH_MODE_RABIN = 0x4,
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SPU2_HASH_MODE_CCM = 0x5,
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SPU2_HASH_MODE_GCM = 0x6,
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SPU2_HASH_MODE_RESERVED = 0x7,
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SPU2_HASH_MODE_LAST
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};
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enum spu2_ret_md_opts {
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SPU2_RET_NO_MD = 0, /* return no metadata */
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SPU2_RET_FMD_OMD = 1, /* return both FMD and OMD */
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SPU2_RET_FMD_ONLY = 2, /* return only FMD */
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SPU2_RET_FMD_OMD_IV = 3, /* return FMD and OMD with just IVs */
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};
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/* Fixed Metadata format */
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struct SPU2_FMD {
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u64 ctrl0;
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u64 ctrl1;
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u64 ctrl2;
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u64 ctrl3;
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};
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#define FMD_SIZE sizeof(struct SPU2_FMD)
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/* Fixed part of request message header length in bytes. Just FMD. */
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#define SPU2_REQ_FIXED_LEN FMD_SIZE
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#define SPU2_HEADER_ALLOC_LEN (SPU_REQ_FIXED_LEN + \
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2 * MAX_KEY_SIZE + 2 * MAX_IV_SIZE)
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/* FMD ctrl0 field masks */
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#define SPU2_CIPH_ENCRYPT_EN 0x1 /* 0: decrypt, 1: encrypt */
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#define SPU2_CIPH_TYPE 0xF0 /* one of spu2_cipher_type */
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#define SPU2_CIPH_TYPE_SHIFT 4
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#define SPU2_CIPH_MODE 0xF00 /* one of spu2_cipher_mode */
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#define SPU2_CIPH_MODE_SHIFT 8
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#define SPU2_CFB_MASK 0x7000 /* cipher feedback mask */
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#define SPU2_CFB_MASK_SHIFT 12
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#define SPU2_PROTO_SEL 0xF00000 /* MACsec, IPsec, TLS... */
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#define SPU2_PROTO_SEL_SHIFT 20
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#define SPU2_HASH_FIRST 0x1000000 /* 1: hash input is input pkt
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* data
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*/
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#define SPU2_CHK_TAG 0x2000000 /* 1: check digest provided */
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#define SPU2_HASH_TYPE 0x1F0000000 /* one of spu2_hash_type */
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#define SPU2_HASH_TYPE_SHIFT 28
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#define SPU2_HASH_MODE 0xF000000000 /* one of spu2_hash_mode */
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#define SPU2_HASH_MODE_SHIFT 36
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#define SPU2_CIPH_PAD_EN 0x100000000000 /* 1: Add pad to end of payload for
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* enc
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*/
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#define SPU2_CIPH_PAD 0xFF000000000000 /* cipher pad value */
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#define SPU2_CIPH_PAD_SHIFT 48
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/* FMD ctrl1 field masks */
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#define SPU2_TAG_LOC 0x1 /* 1: end of payload, 0: undef */
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#define SPU2_HAS_FR_DATA 0x2 /* 1: msg has frame data */
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#define SPU2_HAS_AAD1 0x4 /* 1: msg has AAD1 field */
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#define SPU2_HAS_NAAD 0x8 /* 1: msg has NAAD field */
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#define SPU2_HAS_AAD2 0x10 /* 1: msg has AAD2 field */
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#define SPU2_HAS_ESN 0x20 /* 1: msg has ESN field */
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#define SPU2_HASH_KEY_LEN 0xFF00 /* len of hash key in bytes.
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* HMAC only.
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*/
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#define SPU2_HASH_KEY_LEN_SHIFT 8
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#define SPU2_CIPH_KEY_LEN 0xFF00000 /* len of cipher key in bytes */
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#define SPU2_CIPH_KEY_LEN_SHIFT 20
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#define SPU2_GENIV 0x10000000 /* 1: hw generates IV */
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#define SPU2_HASH_IV 0x20000000 /* 1: IV incl in hash */
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#define SPU2_RET_IV 0x40000000 /* 1: return IV in output msg
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* b4 payload
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*/
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#define SPU2_RET_IV_LEN 0xF00000000 /* length in bytes of IV returned.
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* 0 = 16 bytes
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*/
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#define SPU2_RET_IV_LEN_SHIFT 32
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#define SPU2_IV_OFFSET 0xF000000000 /* gen IV offset */
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#define SPU2_IV_OFFSET_SHIFT 36
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#define SPU2_IV_LEN 0x1F0000000000 /* length of input IV in bytes */
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#define SPU2_IV_LEN_SHIFT 40
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#define SPU2_HASH_TAG_LEN 0x7F000000000000 /* hash tag length in bytes */
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#define SPU2_HASH_TAG_LEN_SHIFT 48
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#define SPU2_RETURN_MD 0x300000000000000 /* return metadata */
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#define SPU2_RETURN_MD_SHIFT 56
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#define SPU2_RETURN_FD 0x400000000000000
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#define SPU2_RETURN_AAD1 0x800000000000000
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#define SPU2_RETURN_NAAD 0x1000000000000000
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#define SPU2_RETURN_AAD2 0x2000000000000000
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#define SPU2_RETURN_PAY 0x4000000000000000 /* return payload */
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/* FMD ctrl2 field masks */
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#define SPU2_AAD1_OFFSET 0xFFF /* byte offset of AAD1 field */
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#define SPU2_AAD1_LEN 0xFF000 /* length of AAD1 in bytes */
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#define SPU2_AAD1_LEN_SHIFT 12
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#define SPU2_AAD2_OFFSET 0xFFF00000 /* byte offset of AAD2 field */
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#define SPU2_AAD2_OFFSET_SHIFT 20
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#define SPU2_PL_OFFSET 0xFFFFFFFF00000000 /* payload offset from AAD2 */
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#define SPU2_PL_OFFSET_SHIFT 32
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/* FMD ctrl3 field masks */
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#define SPU2_PL_LEN 0xFFFFFFFF /* payload length in bytes */
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#define SPU2_TLS_LEN 0xFFFF00000000 /* TLS encrypt: cipher len
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* TLS decrypt: compressed len
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*/
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#define SPU2_TLS_LEN_SHIFT 32
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/*
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* Max value that can be represented in the Payload Length field of the
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* ctrl3 word of FMD.
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*/
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#define SPU2_MAX_PAYLOAD SPU2_PL_LEN
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/* Error values returned in STATUS field of response messages */
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#define SPU2_INVALID_ICV 1
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void spu2_dump_msg_hdr(u8 *buf, unsigned int buf_len);
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u32 spu2_ctx_max_payload(enum spu_cipher_alg cipher_alg,
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enum spu_cipher_mode cipher_mode,
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unsigned int blocksize);
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u32 spu2_payload_length(u8 *spu_hdr);
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u16 spu2_response_hdr_len(u16 auth_key_len, u16 enc_key_len, bool is_hash);
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u16 spu2_hash_pad_len(enum hash_alg hash_alg, enum hash_mode hash_mode,
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u32 chunksize, u16 hash_block_size);
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u32 spu2_gcm_ccm_pad_len(enum spu_cipher_mode cipher_mode,
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unsigned int data_size);
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u32 spu2_assoc_resp_len(enum spu_cipher_mode cipher_mode,
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unsigned int assoc_len, unsigned int iv_len,
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bool is_encrypt);
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u8 spu2_aead_ivlen(enum spu_cipher_mode cipher_mode,
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u16 iv_len);
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enum hash_type spu2_hash_type(u32 src_sent);
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u32 spu2_digest_size(u32 alg_digest_size, enum hash_alg alg,
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enum hash_type htype);
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u32 spu2_create_request(u8 *spu_hdr,
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struct spu_request_opts *req_opts,
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struct spu_cipher_parms *cipher_parms,
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struct spu_hash_parms *hash_parms,
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struct spu_aead_parms *aead_parms,
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unsigned int data_size);
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u16 spu2_cipher_req_init(u8 *spu_hdr, struct spu_cipher_parms *cipher_parms);
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void spu2_cipher_req_finish(u8 *spu_hdr,
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u16 spu_req_hdr_len,
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unsigned int is_inbound,
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struct spu_cipher_parms *cipher_parms,
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bool update_key,
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unsigned int data_size);
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void spu2_request_pad(u8 *pad_start, u32 gcm_padding, u32 hash_pad_len,
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enum hash_alg auth_alg, enum hash_mode auth_mode,
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unsigned int total_sent, u32 status_padding);
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u8 spu2_xts_tweak_in_payload(void);
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u8 spu2_tx_status_len(void);
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u8 spu2_rx_status_len(void);
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int spu2_status_process(u8 *statp);
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void spu2_ccm_update_iv(unsigned int digestsize,
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struct spu_cipher_parms *cipher_parms,
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unsigned int assoclen, unsigned int chunksize,
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bool is_encrypt, bool is_esp);
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u32 spu2_wordalign_padlen(u32 data_size);
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#endif
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