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Nearly each Baikal-T1 IP-core is supposed to have a clock source of particular frequency. But since there are greater than five IP-blocks embedded into the SoC, the CCU PLLs can't fulfill all the needs. Baikal-T1 CCU provides a set of fixed and configurable clock dividers in order to generate a necessary signal for each chip sub-block. This driver creates the of-based hardware clocks for each divider available in Baikal-T1 CCU. The same way as for PLLs we split the functionality up into the clocks operations (gate, ungate, set rate, etc) and hardware clocks declaration/registration procedures. In accordance with the CCU documentation all its dividers are distributed into two CCU sub-blocks: AXI-bus and system devices reference clocks. The former sub-block is used to supply the clocks for AXI-bus interfaces (AXI clock domains) and the later one provides the SoC IP-cores reference clocks. Each sub-block is represented by a dedicated DT node, so they have different compatible strings to distinguish one from another. For some reason CCU provides the dividers of different types. Some dividers can be gateable some can't, some are fixed while the others are variable, some have special divider' limitations, some've got a non-standard register layout and so on. In order to cover all of these cases the hardware clocks driver is designed with an info-descriptor pattern. So there are special static descriptors declared for the dividers of each type with additional flags describing the block peculiarity. These descriptors are then used to create hardware clocks with proper operations. Some CCU dividers provide a way to reset a domain they generate a clock for. So the CCU AXI-bus and CCU system devices clock drivers also perform the reset controller registration. Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru> Cc: Alexey Malahov <Alexey.Malahov@baikalelectronics.ru> Cc: Arnd Bergmann <arnd@arndb.de> Cc: Rob Herring <robh+dt@kernel.org> Cc: linux-mips@vger.kernel.org Cc: devicetree@vger.kernel.org Link: https://lore.kernel.org/r/20200526222056.18072-5-Sergey.Semin@baikalelectronics.ru [sboyd@kernel.org: Drop return from void function, silence sparse warnings about initializing structs with NULL vs. integer] Signed-off-by: Stephen Boyd <sboyd@kernel.org>
43 lines
1.7 KiB
Plaintext
43 lines
1.7 KiB
Plaintext
# SPDX-License-Identifier: GPL-2.0-only
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config CLK_BAIKAL_T1
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bool "Baikal-T1 Clocks Control Unit interface"
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depends on (MIPS_BAIKAL_T1 && OF) || COMPILE_TEST
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default MIPS_BAIKAL_T1
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help
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Clocks Control Unit is the core of Baikal-T1 SoC System Controller
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responsible for the chip subsystems clocking and resetting. It
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consists of multiple global clock domains, which can be reset by
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means of the CCU control registers. These domains and devices placed
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in them are fed with clocks generated by a hierarchy of PLLs,
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configurable and fixed clock dividers. Enable this option to be able
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to select Baikal-T1 CCU PLLs and Dividers drivers.
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if CLK_BAIKAL_T1
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config CLK_BT1_CCU_PLL
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bool "Baikal-T1 CCU PLLs support"
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select MFD_SYSCON
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default MIPS_BAIKAL_T1
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help
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Enable this to support the PLLs embedded into the Baikal-T1 SoC
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System Controller. These are five PLLs placed at the root of the
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clocks hierarchy, right after an external reference oscillator
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(normally of 25MHz). They are used to generate high frequency
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signals, which are either directly wired to the consumers (like
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CPUs, DDR, etc.) or passed over the clock dividers to be only
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then used as an individual reference clock of a target device.
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config CLK_BT1_CCU_DIV
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bool "Baikal-T1 CCU Dividers support"
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select RESET_CONTROLLER
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select MFD_SYSCON
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default MIPS_BAIKAL_T1
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help
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Enable this to support the CCU dividers used to distribute clocks
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between AXI-bus and system devices coming from CCU PLLs of Baikal-T1
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SoC. CCU dividers can be either configurable or with fixed divider,
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either gateable or ungateable. Some of the CCU dividers can be as well
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used to reset the domains they're supplying clock to.
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endif
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