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60faddf6eb
We're going to introduce support to read and write the memory mapped timer registers in the next patch, so push the cp15 read/write functions one level deeper. This simplifies the next patch and makes it clearer what's going on. Cc: Mark Rutland <mark.rutland@arm.com> Cc: Marc Zyngier <Marc.Zyngier@arm.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org> Acked-by: Mark Rutland <mark.rutland@arm.com>
104 lines
2.3 KiB
C
104 lines
2.3 KiB
C
#ifndef __ASMARM_ARCH_TIMER_H
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#define __ASMARM_ARCH_TIMER_H
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#include <asm/barrier.h>
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#include <asm/errno.h>
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#include <linux/clocksource.h>
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#include <linux/init.h>
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#include <linux/types.h>
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#include <clocksource/arm_arch_timer.h>
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#ifdef CONFIG_ARM_ARCH_TIMER
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int arch_timer_arch_init(void);
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/*
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* These register accessors are marked inline so the compiler can
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* nicely work out which register we want, and chuck away the rest of
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* the code. At least it does so with a recent GCC (4.6.3).
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*/
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static __always_inline
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void arch_timer_reg_write_cp15(int access, enum arch_timer_reg reg, u32 val)
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{
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if (access == ARCH_TIMER_PHYS_ACCESS) {
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switch (reg) {
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case ARCH_TIMER_REG_CTRL:
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asm volatile("mcr p15, 0, %0, c14, c2, 1" : : "r" (val));
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break;
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case ARCH_TIMER_REG_TVAL:
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asm volatile("mcr p15, 0, %0, c14, c2, 0" : : "r" (val));
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break;
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}
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} else if (access == ARCH_TIMER_VIRT_ACCESS) {
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switch (reg) {
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case ARCH_TIMER_REG_CTRL:
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asm volatile("mcr p15, 0, %0, c14, c3, 1" : : "r" (val));
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break;
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case ARCH_TIMER_REG_TVAL:
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asm volatile("mcr p15, 0, %0, c14, c3, 0" : : "r" (val));
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break;
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}
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}
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isb();
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}
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static __always_inline
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u32 arch_timer_reg_read_cp15(int access, enum arch_timer_reg reg)
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{
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u32 val = 0;
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if (access == ARCH_TIMER_PHYS_ACCESS) {
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switch (reg) {
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case ARCH_TIMER_REG_CTRL:
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asm volatile("mrc p15, 0, %0, c14, c2, 1" : "=r" (val));
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break;
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case ARCH_TIMER_REG_TVAL:
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asm volatile("mrc p15, 0, %0, c14, c2, 0" : "=r" (val));
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break;
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}
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} else if (access == ARCH_TIMER_VIRT_ACCESS) {
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switch (reg) {
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case ARCH_TIMER_REG_CTRL:
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asm volatile("mrc p15, 0, %0, c14, c3, 1" : "=r" (val));
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break;
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case ARCH_TIMER_REG_TVAL:
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asm volatile("mrc p15, 0, %0, c14, c3, 0" : "=r" (val));
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break;
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}
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}
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return val;
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}
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static inline u32 arch_timer_get_cntfrq(void)
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{
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u32 val;
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asm volatile("mrc p15, 0, %0, c14, c0, 0" : "=r" (val));
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return val;
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}
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static inline u64 arch_counter_get_cntvct(void)
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{
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u64 cval;
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isb();
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asm volatile("mrrc p15, 1, %Q0, %R0, c14" : "=r" (cval));
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return cval;
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}
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static inline void __cpuinit arch_counter_set_user_access(void)
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{
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u32 cntkctl;
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asm volatile("mrc p15, 0, %0, c14, c1, 0" : "=r" (cntkctl));
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/* disable user access to everything */
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cntkctl &= ~((3 << 8) | (7 << 0));
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asm volatile("mcr p15, 0, %0, c14, c1, 0" : : "r" (cntkctl));
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}
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#endif
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#endif
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