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55bf9267dd
Turn the init sequence of s3c24xx_register_baseclocks(xtal); s3c64xx_register_clocks(); s3c6400_register_clocks(S3C6410_CLKDIV0_ARM_MASK); into a single call as this is now contained within one file. Signed-off-by: Ben Dooks <ben-linux@fluff.org>
802 lines
18 KiB
C
802 lines
18 KiB
C
/* linux/arch/arm/plat-s3c64xx/clock.c
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*
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* Copyright 2008 Openmoko, Inc.
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* Copyright 2008 Simtec Electronics
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* Ben Dooks <ben@simtec.co.uk>
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* http://armlinux.simtec.co.uk/
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*
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* S3C64XX Base clock support
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/init.h>
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#include <linux/module.h>
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#include <linux/interrupt.h>
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#include <linux/ioport.h>
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#include <linux/clk.h>
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#include <linux/err.h>
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#include <linux/io.h>
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#include <mach/hardware.h>
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#include <mach/map.h>
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#include <mach/regs-sys.h>
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#include <mach/regs-clock.h>
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#include <mach/pll.h>
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#include <plat/cpu.h>
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#include <plat/devs.h>
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#include <plat/cpu-freq.h>
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#include <plat/clock.h>
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#include <plat/clock-clksrc.h>
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/* fin_apll, fin_mpll and fin_epll are all the same clock, which we call
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* ext_xtal_mux for want of an actual name from the manual.
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*/
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static struct clk clk_ext_xtal_mux = {
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.name = "ext_xtal",
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.id = -1,
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};
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#define clk_fin_apll clk_ext_xtal_mux
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#define clk_fin_mpll clk_ext_xtal_mux
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#define clk_fin_epll clk_ext_xtal_mux
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#define clk_fout_mpll clk_mpll
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#define clk_fout_epll clk_epll
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struct clk clk_h2 = {
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.name = "hclk2",
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.id = -1,
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.rate = 0,
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};
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struct clk clk_27m = {
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.name = "clk_27m",
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.id = -1,
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.rate = 27000000,
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};
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static int clk_48m_ctrl(struct clk *clk, int enable)
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{
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unsigned long flags;
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u32 val;
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/* can't rely on clock lock, this register has other usages */
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local_irq_save(flags);
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val = __raw_readl(S3C64XX_OTHERS);
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if (enable)
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val |= S3C64XX_OTHERS_USBMASK;
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else
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val &= ~S3C64XX_OTHERS_USBMASK;
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__raw_writel(val, S3C64XX_OTHERS);
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local_irq_restore(flags);
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return 0;
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}
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struct clk clk_48m = {
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.name = "clk_48m",
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.id = -1,
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.rate = 48000000,
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.enable = clk_48m_ctrl,
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};
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static int inline s3c64xx_gate(void __iomem *reg,
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struct clk *clk,
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int enable)
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{
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unsigned int ctrlbit = clk->ctrlbit;
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u32 con;
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con = __raw_readl(reg);
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if (enable)
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con |= ctrlbit;
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else
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con &= ~ctrlbit;
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__raw_writel(con, reg);
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return 0;
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}
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static int s3c64xx_pclk_ctrl(struct clk *clk, int enable)
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{
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return s3c64xx_gate(S3C_PCLK_GATE, clk, enable);
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}
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static int s3c64xx_hclk_ctrl(struct clk *clk, int enable)
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{
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return s3c64xx_gate(S3C_HCLK_GATE, clk, enable);
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}
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int s3c64xx_sclk_ctrl(struct clk *clk, int enable)
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{
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return s3c64xx_gate(S3C_SCLK_GATE, clk, enable);
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}
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static struct clk init_clocks_disable[] = {
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{
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.name = "nand",
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.id = -1,
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.parent = &clk_h,
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}, {
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.name = "adc",
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.id = -1,
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.parent = &clk_p,
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.enable = s3c64xx_pclk_ctrl,
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.ctrlbit = S3C_CLKCON_PCLK_TSADC,
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}, {
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.name = "i2c",
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.id = -1,
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.parent = &clk_p,
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.enable = s3c64xx_pclk_ctrl,
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.ctrlbit = S3C_CLKCON_PCLK_IIC,
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}, {
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.name = "iis",
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.id = 0,
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.parent = &clk_p,
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.enable = s3c64xx_pclk_ctrl,
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.ctrlbit = S3C_CLKCON_PCLK_IIS0,
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}, {
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.name = "iis",
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.id = 1,
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.parent = &clk_p,
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.enable = s3c64xx_pclk_ctrl,
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.ctrlbit = S3C_CLKCON_PCLK_IIS1,
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}, {
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.name = "spi",
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.id = 0,
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.parent = &clk_p,
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.enable = s3c64xx_pclk_ctrl,
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.ctrlbit = S3C_CLKCON_PCLK_SPI0,
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}, {
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.name = "spi",
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.id = 1,
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.parent = &clk_p,
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.enable = s3c64xx_pclk_ctrl,
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.ctrlbit = S3C_CLKCON_PCLK_SPI1,
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}, {
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.name = "spi_48m",
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.id = 0,
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.parent = &clk_48m,
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.enable = s3c64xx_sclk_ctrl,
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.ctrlbit = S3C_CLKCON_SCLK_SPI0_48,
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}, {
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.name = "spi_48m",
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.id = 1,
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.parent = &clk_48m,
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.enable = s3c64xx_sclk_ctrl,
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.ctrlbit = S3C_CLKCON_SCLK_SPI1_48,
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}, {
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.name = "48m",
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.id = 0,
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.parent = &clk_48m,
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.enable = s3c64xx_sclk_ctrl,
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.ctrlbit = S3C_CLKCON_SCLK_MMC0_48,
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}, {
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.name = "48m",
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.id = 1,
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.parent = &clk_48m,
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.enable = s3c64xx_sclk_ctrl,
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.ctrlbit = S3C_CLKCON_SCLK_MMC1_48,
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}, {
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.name = "48m",
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.id = 2,
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.parent = &clk_48m,
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.enable = s3c64xx_sclk_ctrl,
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.ctrlbit = S3C_CLKCON_SCLK_MMC2_48,
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}, {
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.name = "dma0",
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.id = -1,
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.parent = &clk_h,
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.enable = s3c64xx_hclk_ctrl,
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.ctrlbit = S3C_CLKCON_HCLK_DMA0,
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}, {
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.name = "dma1",
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.id = -1,
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.parent = &clk_h,
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.enable = s3c64xx_hclk_ctrl,
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.ctrlbit = S3C_CLKCON_HCLK_DMA1,
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},
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};
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static struct clk init_clocks[] = {
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{
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.name = "lcd",
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.id = -1,
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.parent = &clk_h,
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.enable = s3c64xx_hclk_ctrl,
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.ctrlbit = S3C_CLKCON_HCLK_LCD,
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}, {
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.name = "gpio",
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.id = -1,
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.parent = &clk_p,
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.enable = s3c64xx_pclk_ctrl,
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.ctrlbit = S3C_CLKCON_PCLK_GPIO,
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}, {
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.name = "usb-host",
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.id = -1,
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.parent = &clk_h,
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.enable = s3c64xx_hclk_ctrl,
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.ctrlbit = S3C_CLKCON_HCLK_UHOST,
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}, {
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.name = "hsmmc",
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.id = 0,
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.parent = &clk_h,
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.enable = s3c64xx_hclk_ctrl,
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.ctrlbit = S3C_CLKCON_HCLK_HSMMC0,
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}, {
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.name = "hsmmc",
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.id = 1,
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.parent = &clk_h,
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.enable = s3c64xx_hclk_ctrl,
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.ctrlbit = S3C_CLKCON_HCLK_HSMMC1,
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}, {
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.name = "hsmmc",
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.id = 2,
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.parent = &clk_h,
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.enable = s3c64xx_hclk_ctrl,
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.ctrlbit = S3C_CLKCON_HCLK_HSMMC2,
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}, {
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.name = "timers",
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.id = -1,
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.parent = &clk_p,
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.enable = s3c64xx_pclk_ctrl,
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.ctrlbit = S3C_CLKCON_PCLK_PWM,
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}, {
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.name = "uart",
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.id = 0,
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.parent = &clk_p,
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.enable = s3c64xx_pclk_ctrl,
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.ctrlbit = S3C_CLKCON_PCLK_UART0,
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}, {
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.name = "uart",
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.id = 1,
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.parent = &clk_p,
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.enable = s3c64xx_pclk_ctrl,
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.ctrlbit = S3C_CLKCON_PCLK_UART1,
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}, {
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.name = "uart",
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.id = 2,
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.parent = &clk_p,
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.enable = s3c64xx_pclk_ctrl,
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.ctrlbit = S3C_CLKCON_PCLK_UART2,
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}, {
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.name = "uart",
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.id = 3,
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.parent = &clk_p,
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.enable = s3c64xx_pclk_ctrl,
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.ctrlbit = S3C_CLKCON_PCLK_UART3,
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}, {
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.name = "rtc",
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.id = -1,
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.parent = &clk_p,
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.enable = s3c64xx_pclk_ctrl,
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.ctrlbit = S3C_CLKCON_PCLK_RTC,
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}, {
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.name = "watchdog",
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.id = -1,
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.parent = &clk_p,
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.ctrlbit = S3C_CLKCON_PCLK_WDT,
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}, {
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.name = "ac97",
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.id = -1,
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.parent = &clk_p,
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.ctrlbit = S3C_CLKCON_PCLK_AC97,
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}
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};
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static struct clk clk_fout_apll = {
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.name = "fout_apll",
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.id = -1,
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};
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static struct clk *clk_src_apll_list[] = {
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[0] = &clk_fin_apll,
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[1] = &clk_fout_apll,
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};
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static struct clksrc_sources clk_src_apll = {
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.sources = clk_src_apll_list,
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.nr_sources = ARRAY_SIZE(clk_src_apll_list),
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};
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static struct clksrc_clk clk_mout_apll = {
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.clk = {
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.name = "mout_apll",
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.id = -1,
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},
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.reg_src = { .reg = S3C_CLK_SRC, .shift = 0, .size = 1 },
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.sources = &clk_src_apll,
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};
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static struct clk *clk_src_epll_list[] = {
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[0] = &clk_fin_epll,
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[1] = &clk_fout_epll,
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};
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static struct clksrc_sources clk_src_epll = {
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.sources = clk_src_epll_list,
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.nr_sources = ARRAY_SIZE(clk_src_epll_list),
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};
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static struct clksrc_clk clk_mout_epll = {
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.clk = {
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.name = "mout_epll",
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.id = -1,
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},
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.reg_src = { .reg = S3C_CLK_SRC, .shift = 2, .size = 1 },
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.sources = &clk_src_epll,
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};
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static struct clk *clk_src_mpll_list[] = {
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[0] = &clk_fin_mpll,
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[1] = &clk_fout_mpll,
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};
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static struct clksrc_sources clk_src_mpll = {
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.sources = clk_src_mpll_list,
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.nr_sources = ARRAY_SIZE(clk_src_mpll_list),
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};
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static struct clksrc_clk clk_mout_mpll = {
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.clk = {
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.name = "mout_mpll",
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.id = -1,
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},
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.reg_src = { .reg = S3C_CLK_SRC, .shift = 1, .size = 1 },
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.sources = &clk_src_mpll,
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};
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static unsigned int armclk_mask;
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static unsigned long s3c64xx_clk_arm_get_rate(struct clk *clk)
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{
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unsigned long rate = clk_get_rate(clk->parent);
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u32 clkdiv;
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/* divisor mask starts at bit0, so no need to shift */
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clkdiv = __raw_readl(S3C_CLK_DIV0) & armclk_mask;
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return rate / (clkdiv + 1);
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}
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static unsigned long s3c64xx_clk_arm_round_rate(struct clk *clk,
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unsigned long rate)
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{
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unsigned long parent = clk_get_rate(clk->parent);
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u32 div;
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if (parent < rate)
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return parent;
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div = (parent / rate) - 1;
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if (div > armclk_mask)
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div = armclk_mask;
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return parent / (div + 1);
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}
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static int s3c64xx_clk_arm_set_rate(struct clk *clk, unsigned long rate)
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{
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unsigned long parent = clk_get_rate(clk->parent);
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u32 div;
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u32 val;
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if (rate < parent / (armclk_mask + 1))
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return -EINVAL;
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rate = clk_round_rate(clk, rate);
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div = clk_get_rate(clk->parent) / rate;
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val = __raw_readl(S3C_CLK_DIV0);
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val &= ~armclk_mask;
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val |= (div - 1);
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__raw_writel(val, S3C_CLK_DIV0);
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return 0;
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}
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static struct clk clk_arm = {
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.name = "armclk",
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.id = -1,
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.parent = &clk_mout_apll.clk,
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.ops = &(struct clk_ops) {
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.get_rate = s3c64xx_clk_arm_get_rate,
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.set_rate = s3c64xx_clk_arm_set_rate,
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.round_rate = s3c64xx_clk_arm_round_rate,
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},
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};
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static unsigned long s3c64xx_clk_doutmpll_get_rate(struct clk *clk)
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{
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unsigned long rate = clk_get_rate(clk->parent);
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printk(KERN_DEBUG "%s: parent is %ld\n", __func__, rate);
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if (__raw_readl(S3C_CLK_DIV0) & S3C6400_CLKDIV0_MPLL_MASK)
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rate /= 2;
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return rate;
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}
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static struct clk_ops clk_dout_ops = {
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.get_rate = s3c64xx_clk_doutmpll_get_rate,
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};
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static struct clk clk_dout_mpll = {
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.name = "dout_mpll",
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.id = -1,
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.parent = &clk_mout_mpll.clk,
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.ops = &clk_dout_ops,
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};
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static struct clk *clkset_spi_mmc_list[] = {
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&clk_mout_epll.clk,
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&clk_dout_mpll,
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&clk_fin_epll,
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&clk_27m,
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};
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static struct clksrc_sources clkset_spi_mmc = {
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.sources = clkset_spi_mmc_list,
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.nr_sources = ARRAY_SIZE(clkset_spi_mmc_list),
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};
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static struct clk *clkset_irda_list[] = {
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&clk_mout_epll.clk,
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&clk_dout_mpll,
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NULL,
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&clk_27m,
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};
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static struct clksrc_sources clkset_irda = {
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.sources = clkset_irda_list,
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.nr_sources = ARRAY_SIZE(clkset_irda_list),
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};
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static struct clk *clkset_uart_list[] = {
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&clk_mout_epll.clk,
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&clk_dout_mpll,
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NULL,
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NULL
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};
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static struct clksrc_sources clkset_uart = {
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.sources = clkset_uart_list,
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.nr_sources = ARRAY_SIZE(clkset_uart_list),
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};
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static struct clk *clkset_uhost_list[] = {
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&clk_48m,
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&clk_mout_epll.clk,
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&clk_dout_mpll,
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&clk_fin_epll,
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};
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static struct clksrc_sources clkset_uhost = {
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.sources = clkset_uhost_list,
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.nr_sources = ARRAY_SIZE(clkset_uhost_list),
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};
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/* The peripheral clocks are all controlled via clocksource followed
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* by an optional divider and gate stage. We currently roll this into
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* one clock which hides the intermediate clock from the mux.
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*
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* Note, the JPEG clock can only be an even divider...
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*
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* The scaler and LCD clocks depend on the S3C64XX version, and also
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* have a common parent divisor so are not included here.
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*/
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/* clocks that feed other parts of the clock source tree */
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static struct clk clk_iis_cd0 = {
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.name = "iis_cdclk0",
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.id = -1,
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};
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static struct clk clk_iis_cd1 = {
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.name = "iis_cdclk1",
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.id = -1,
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};
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static struct clk clk_pcm_cd = {
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.name = "pcm_cdclk",
|
|
.id = -1,
|
|
};
|
|
|
|
static struct clk *clkset_audio0_list[] = {
|
|
[0] = &clk_mout_epll.clk,
|
|
[1] = &clk_dout_mpll,
|
|
[2] = &clk_fin_epll,
|
|
[3] = &clk_iis_cd0,
|
|
[4] = &clk_pcm_cd,
|
|
};
|
|
|
|
static struct clksrc_sources clkset_audio0 = {
|
|
.sources = clkset_audio0_list,
|
|
.nr_sources = ARRAY_SIZE(clkset_audio0_list),
|
|
};
|
|
|
|
static struct clk *clkset_audio1_list[] = {
|
|
[0] = &clk_mout_epll.clk,
|
|
[1] = &clk_dout_mpll,
|
|
[2] = &clk_fin_epll,
|
|
[3] = &clk_iis_cd1,
|
|
[4] = &clk_pcm_cd,
|
|
};
|
|
|
|
static struct clksrc_sources clkset_audio1 = {
|
|
.sources = clkset_audio1_list,
|
|
.nr_sources = ARRAY_SIZE(clkset_audio1_list),
|
|
};
|
|
|
|
static struct clk *clkset_camif_list[] = {
|
|
&clk_h2,
|
|
};
|
|
|
|
static struct clksrc_sources clkset_camif = {
|
|
.sources = clkset_camif_list,
|
|
.nr_sources = ARRAY_SIZE(clkset_camif_list),
|
|
};
|
|
|
|
static struct clksrc_clk clksrcs[] = {
|
|
{
|
|
.clk = {
|
|
.name = "mmc_bus",
|
|
.id = 0,
|
|
.ctrlbit = S3C_CLKCON_SCLK_MMC0,
|
|
.enable = s3c64xx_sclk_ctrl,
|
|
},
|
|
.reg_src = { .reg = S3C_CLK_SRC, .shift = 18, .size = 2 },
|
|
.reg_div = { .reg = S3C_CLK_DIV1, .shift = 0, .size = 4 },
|
|
.sources = &clkset_spi_mmc,
|
|
}, {
|
|
.clk = {
|
|
.name = "mmc_bus",
|
|
.id = 1,
|
|
.ctrlbit = S3C_CLKCON_SCLK_MMC1,
|
|
.enable = s3c64xx_sclk_ctrl,
|
|
},
|
|
.reg_src = { .reg = S3C_CLK_SRC, .shift = 20, .size = 2 },
|
|
.reg_div = { .reg = S3C_CLK_DIV1, .shift = 4, .size = 4 },
|
|
.sources = &clkset_spi_mmc,
|
|
}, {
|
|
.clk = {
|
|
.name = "mmc_bus",
|
|
.id = 2,
|
|
.ctrlbit = S3C_CLKCON_SCLK_MMC2,
|
|
.enable = s3c64xx_sclk_ctrl,
|
|
},
|
|
.reg_src = { .reg = S3C_CLK_SRC, .shift = 22, .size = 2 },
|
|
.reg_div = { .reg = S3C_CLK_DIV1, .shift = 8, .size = 4 },
|
|
.sources = &clkset_spi_mmc,
|
|
}, {
|
|
.clk = {
|
|
.name = "usb-bus-host",
|
|
.id = -1,
|
|
.ctrlbit = S3C_CLKCON_SCLK_UHOST,
|
|
.enable = s3c64xx_sclk_ctrl,
|
|
},
|
|
.reg_src = { .reg = S3C_CLK_SRC, .shift = 5, .size = 2 },
|
|
.reg_div = { .reg = S3C_CLK_DIV1, .shift = 20, .size = 4 },
|
|
.sources = &clkset_uhost,
|
|
}, {
|
|
.clk = {
|
|
.name = "uclk1",
|
|
.id = -1,
|
|
.ctrlbit = S3C_CLKCON_SCLK_UART,
|
|
.enable = s3c64xx_sclk_ctrl,
|
|
},
|
|
.reg_src = { .reg = S3C_CLK_SRC, .shift = 13, .size = 1 },
|
|
.reg_div = { .reg = S3C_CLK_DIV2, .shift = 16, .size = 4 },
|
|
.sources = &clkset_uart,
|
|
}, {
|
|
/* Where does UCLK0 come from? */
|
|
.clk = {
|
|
.name = "spi-bus",
|
|
.id = 0,
|
|
.ctrlbit = S3C_CLKCON_SCLK_SPI0,
|
|
.enable = s3c64xx_sclk_ctrl,
|
|
},
|
|
.reg_src = { .reg = S3C_CLK_SRC, .shift = 14, .size = 2 },
|
|
.reg_div = { .reg = S3C_CLK_DIV2, .shift = 0, .size = 4 },
|
|
.sources = &clkset_spi_mmc,
|
|
}, {
|
|
.clk = {
|
|
.name = "spi-bus",
|
|
.id = 1,
|
|
.ctrlbit = S3C_CLKCON_SCLK_SPI1,
|
|
.enable = s3c64xx_sclk_ctrl,
|
|
},
|
|
.reg_src = { .reg = S3C_CLK_SRC, .shift = 16, .size = 2 },
|
|
.reg_div = { .reg = S3C_CLK_DIV2, .shift = 4, .size = 4 },
|
|
.sources = &clkset_spi_mmc,
|
|
}, {
|
|
.clk = {
|
|
.name = "audio-bus",
|
|
.id = 0,
|
|
.ctrlbit = S3C_CLKCON_SCLK_AUDIO0,
|
|
.enable = s3c64xx_sclk_ctrl,
|
|
},
|
|
.reg_src = { .reg = S3C_CLK_SRC, .shift = 7, .size = 3 },
|
|
.reg_div = { .reg = S3C_CLK_DIV2, .shift = 8, .size = 4 },
|
|
.sources = &clkset_audio0,
|
|
}, {
|
|
.clk = {
|
|
.name = "audio-bus",
|
|
.id = 1,
|
|
.ctrlbit = S3C_CLKCON_SCLK_AUDIO1,
|
|
.enable = s3c64xx_sclk_ctrl,
|
|
},
|
|
.reg_src = { .reg = S3C_CLK_SRC, .shift = 10, .size = 3 },
|
|
.reg_div = { .reg = S3C_CLK_DIV2, .shift = 12, .size = 4 },
|
|
.sources = &clkset_audio1,
|
|
}, {
|
|
.clk = {
|
|
.name = "irda-bus",
|
|
.id = 0,
|
|
.ctrlbit = S3C_CLKCON_SCLK_IRDA,
|
|
.enable = s3c64xx_sclk_ctrl,
|
|
},
|
|
.reg_src = { .reg = S3C_CLK_SRC, .shift = 24, .size = 2 },
|
|
.reg_div = { .reg = S3C_CLK_DIV2, .shift = 20, .size = 4 },
|
|
.sources = &clkset_irda,
|
|
}, {
|
|
.clk = {
|
|
.name = "camera",
|
|
.id = -1,
|
|
.ctrlbit = S3C_CLKCON_SCLK_CAM,
|
|
.enable = s3c64xx_sclk_ctrl,
|
|
},
|
|
.reg_div = { .reg = S3C_CLK_DIV0, .shift = 20, .size = 4 },
|
|
.reg_src = { .reg = NULL, .shift = 0, .size = 0 },
|
|
.sources = &clkset_camif,
|
|
},
|
|
};
|
|
|
|
/* Clock initialisation code */
|
|
|
|
static struct clksrc_clk *init_parents[] = {
|
|
&clk_mout_apll,
|
|
&clk_mout_epll,
|
|
&clk_mout_mpll,
|
|
};
|
|
|
|
#define GET_DIV(clk, field) ((((clk) & field##_MASK) >> field##_SHIFT) + 1)
|
|
|
|
void __init_or_cpufreq s3c6400_setup_clocks(void)
|
|
{
|
|
struct clk *xtal_clk;
|
|
unsigned long xtal;
|
|
unsigned long fclk;
|
|
unsigned long hclk;
|
|
unsigned long hclk2;
|
|
unsigned long pclk;
|
|
unsigned long epll;
|
|
unsigned long apll;
|
|
unsigned long mpll;
|
|
unsigned int ptr;
|
|
u32 clkdiv0;
|
|
|
|
printk(KERN_DEBUG "%s: registering clocks\n", __func__);
|
|
|
|
clkdiv0 = __raw_readl(S3C_CLK_DIV0);
|
|
printk(KERN_DEBUG "%s: clkdiv0 = %08x\n", __func__, clkdiv0);
|
|
|
|
xtal_clk = clk_get(NULL, "xtal");
|
|
BUG_ON(IS_ERR(xtal_clk));
|
|
|
|
xtal = clk_get_rate(xtal_clk);
|
|
clk_put(xtal_clk);
|
|
|
|
printk(KERN_DEBUG "%s: xtal is %ld\n", __func__, xtal);
|
|
|
|
/* For now assume the mux always selects the crystal */
|
|
clk_ext_xtal_mux.parent = xtal_clk;
|
|
|
|
epll = s3c6400_get_epll(xtal);
|
|
mpll = s3c6400_get_pll(xtal, __raw_readl(S3C_MPLL_CON));
|
|
apll = s3c6400_get_pll(xtal, __raw_readl(S3C_APLL_CON));
|
|
|
|
fclk = mpll;
|
|
|
|
printk(KERN_INFO "S3C64XX: PLL settings, A=%ld, M=%ld, E=%ld\n",
|
|
apll, mpll, epll);
|
|
|
|
hclk2 = mpll / GET_DIV(clkdiv0, S3C6400_CLKDIV0_HCLK2);
|
|
hclk = hclk2 / GET_DIV(clkdiv0, S3C6400_CLKDIV0_HCLK);
|
|
pclk = hclk2 / GET_DIV(clkdiv0, S3C6400_CLKDIV0_PCLK);
|
|
|
|
printk(KERN_INFO "S3C64XX: HCLK2=%ld, HCLK=%ld, PCLK=%ld\n",
|
|
hclk2, hclk, pclk);
|
|
|
|
clk_fout_mpll.rate = mpll;
|
|
clk_fout_epll.rate = epll;
|
|
clk_fout_apll.rate = apll;
|
|
|
|
clk_h2.rate = hclk2;
|
|
clk_h.rate = hclk;
|
|
clk_p.rate = pclk;
|
|
clk_f.rate = fclk;
|
|
|
|
for (ptr = 0; ptr < ARRAY_SIZE(init_parents); ptr++)
|
|
s3c_set_clksrc(init_parents[ptr], true);
|
|
|
|
for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++)
|
|
s3c_set_clksrc(&clksrcs[ptr], true);
|
|
}
|
|
|
|
static struct clk *clks1[] __initdata = {
|
|
&clk_ext_xtal_mux,
|
|
&clk_iis_cd0,
|
|
&clk_iis_cd1,
|
|
&clk_pcm_cd,
|
|
&clk_mout_epll.clk,
|
|
&clk_mout_mpll.clk,
|
|
&clk_dout_mpll,
|
|
&clk_arm,
|
|
};
|
|
|
|
static struct clk *clks[] __initdata = {
|
|
&clk_ext,
|
|
&clk_epll,
|
|
&clk_27m,
|
|
&clk_48m,
|
|
&clk_h2,
|
|
};
|
|
|
|
/**
|
|
* s3c64xx_register_clocks - register clocks for s3c6400 and s3c6410
|
|
* @xtal: The rate for the clock crystal feeding the PLLs.
|
|
* @armclk_divlimit: Divisor mask for ARMCLK.
|
|
*
|
|
* Register the clocks for the S3C6400 and S3C6410 SoC range, such
|
|
* as ARMCLK as well as the necessary parent clocks.
|
|
*
|
|
* This call does not setup the clocks, which is left to the
|
|
* s3c6400_setup_clocks() call which may be needed by the cpufreq
|
|
* or resume code to re-set the clocks if the bootloader has changed
|
|
* them.
|
|
*/
|
|
void __init s3c64xx_register_clocks(unsigned long xtal,
|
|
unsigned armclk_divlimit)
|
|
{
|
|
struct clk *clkp;
|
|
int ret;
|
|
int ptr;
|
|
|
|
armclk_mask = armclk_divlimit;
|
|
|
|
s3c24xx_register_baseclocks(xtal);
|
|
s3c24xx_register_clocks(clks, ARRAY_SIZE(clks));
|
|
|
|
s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks));
|
|
|
|
clkp = init_clocks_disable;
|
|
for (ptr = 0; ptr < ARRAY_SIZE(init_clocks_disable); ptr++, clkp++) {
|
|
|
|
ret = s3c24xx_register_clock(clkp);
|
|
if (ret < 0) {
|
|
printk(KERN_ERR "Failed to register clock %s (%d)\n",
|
|
clkp->name, ret);
|
|
}
|
|
|
|
(clkp->enable)(clkp, 0);
|
|
}
|
|
|
|
s3c24xx_register_clocks(clks1, ARRAY_SIZE(clks1));
|
|
s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
|
|
s3c_pwmclk_init();
|
|
}
|