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c076ada4e4
On transactions with n>=2 bytes, the controller actually wrongly clocks in n+1 bytes. This is caused by the (wrong) assumption that RFE in the Status Register is 1 iff there is no byte already ordered (via a dummy TX byte). This lead to the implementation of synchronized byte ordering, e.g.: Dummy-TX - RX - Dummy-TX - RX - ... But since RFE actually stays high after some Dummy-TX, it rather looks like: Dummy-TX - Dummy-TX - RX - Dummy-TX - RX - (RX) The last RX byte is clocked in by the bus controller, but ignored by the kernel when filling the userspace buffer. This patch fixes the issue by asking for RX via Dummy-TX asynchronously. Introducing a separate counter for TX bytes. Signed-off-by: Roland Stigge <stigge@antcom.de> Signed-off-by: Wolfram Sang <w.sang@pengutronix.de>
40 lines
943 B
C
40 lines
943 B
C
/*
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* Header file for I2C support on PNX010x/4008.
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*
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* Author: Dennis Kovalev <dkovalev@ru.mvista.com>
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*
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* 2004-2006 (c) MontaVista Software, Inc. This file is licensed under
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* the terms of the GNU General Public License version 2. This program
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* is licensed "as is" without any warranty of any kind, whether express
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* or implied.
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*/
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#ifndef __I2C_PNX_H__
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#define __I2C_PNX_H__
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struct platform_device;
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struct clk;
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struct i2c_pnx_mif {
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int ret; /* Return value */
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int mode; /* Interface mode */
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struct completion complete; /* I/O completion */
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struct timer_list timer; /* Timeout */
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u8 * buf; /* Data buffer */
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int len; /* Length of data buffer */
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int order; /* RX Bytes to order via TX */
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};
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struct i2c_pnx_algo_data {
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void __iomem *ioaddr;
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struct i2c_pnx_mif mif;
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int last;
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struct clk *clk;
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struct i2c_adapter adapter;
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phys_addr_t base;
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int irq;
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u32 timeout;
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};
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#endif /* __I2C_PNX_H__ */
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