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linux-next/drivers/clk/tegra/clk-id.h
Dmitry Osipenko 5bf5861d6e clk: tegra: Fix duplicated SE clock entry 
The periph_clks[] array contains duplicated entry for Security Engine
clock which was meant to be defined for T210, but it wasn't added
properly. This patch corrects the T210 SE entry and fixes the following
error message on T114/T124: "Tegra clk 127: register failed with -17".

Fixes: dc37fec483 ("clk: tegra: periph: Add new periph clks and muxes for Tegra210")
Tested-by Nicolas Chauvet <kwizart@gmail.com>
Reported-by Nicolas Chauvet <kwizart@gmail.com>
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Link: https://lore.kernel.org/r/20201025224212.7790-1-digetx@gmail.com
Acked-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-12-10 12:51:59 -08:00

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/* SPDX-License-Identifier: GPL-2.0 */
/*
* This header provides IDs for clocks common between several Tegra SoCs
*/
#ifndef _TEGRA_CLK_ID_H
#define _TEGRA_CLK_ID_H
enum clk_id {
tegra_clk_actmon,
tegra_clk_adx,
tegra_clk_adx1,
tegra_clk_afi,
tegra_clk_amx,
tegra_clk_amx1,
tegra_clk_apb2ape,
tegra_clk_ahbdma,
tegra_clk_apbdma,
tegra_clk_apbif,
tegra_clk_ape,
tegra_clk_audio0,
tegra_clk_audio0_2x,
tegra_clk_audio0_mux,
tegra_clk_audio1,
tegra_clk_audio1_2x,
tegra_clk_audio1_mux,
tegra_clk_audio2,
tegra_clk_audio2_2x,
tegra_clk_audio2_mux,
tegra_clk_audio3,
tegra_clk_audio3_2x,
tegra_clk_audio3_mux,
tegra_clk_audio4,
tegra_clk_audio4_2x,
tegra_clk_audio4_mux,
tegra_clk_bsea,
tegra_clk_bsev,
tegra_clk_cclk_g,
tegra_clk_cclk_lp,
tegra_clk_cilab,
tegra_clk_cilcd,
tegra_clk_cile,
tegra_clk_clk_32k,
tegra_clk_clk72Mhz,
tegra_clk_clk72Mhz_8,
tegra_clk_clk_m,
tegra_clk_osc,
tegra_clk_osc_div2,
tegra_clk_osc_div4,
tegra_clk_cml0,
tegra_clk_cml1,
tegra_clk_csi,
tegra_clk_csite,
tegra_clk_csite_8,
tegra_clk_csus,
tegra_clk_cve,
tegra_clk_dam0,
tegra_clk_dam1,
tegra_clk_dam2,
tegra_clk_d_audio,
tegra_clk_dbgapb,
tegra_clk_dds,
tegra_clk_dfll_ref,
tegra_clk_dfll_soc,
tegra_clk_disp1,
tegra_clk_disp1_8,
tegra_clk_disp2,
tegra_clk_disp2_8,
tegra_clk_dp2,
tegra_clk_dpaux,
tegra_clk_dpaux1,
tegra_clk_dsialp,
tegra_clk_dsia_mux,
tegra_clk_dsiblp,
tegra_clk_dsib_mux,
tegra_clk_dtv,
tegra_clk_emc,
tegra_clk_entropy,
tegra_clk_entropy_8,
tegra_clk_epp,
tegra_clk_epp_8,
tegra_clk_extern1,
tegra_clk_extern2,
tegra_clk_extern3,
tegra_clk_fuse,
tegra_clk_fuse_burn,
tegra_clk_gpu,
tegra_clk_gr2d,
tegra_clk_gr2d_8,
tegra_clk_gr3d,
tegra_clk_gr3d_8,
tegra_clk_hclk,
tegra_clk_hda,
tegra_clk_hda_8,
tegra_clk_hda2codec_2x,
tegra_clk_hda2codec_2x_8,
tegra_clk_hda2hdmi,
tegra_clk_hdmi,
tegra_clk_hdmi_audio,
tegra_clk_host1x,
tegra_clk_host1x_8,
tegra_clk_host1x_9,
tegra_clk_hsic_trk,
tegra_clk_i2c1,
tegra_clk_i2c2,
tegra_clk_i2c3,
tegra_clk_i2c4,
tegra_clk_i2c5,
tegra_clk_i2c6,
tegra_clk_i2cslow,
tegra_clk_i2s0,
tegra_clk_i2s0_sync,
tegra_clk_i2s1,
tegra_clk_i2s1_sync,
tegra_clk_i2s2,
tegra_clk_i2s2_sync,
tegra_clk_i2s3,
tegra_clk_i2s3_sync,
tegra_clk_i2s4,
tegra_clk_i2s4_sync,
tegra_clk_isp,
tegra_clk_isp_8,
tegra_clk_isp_9,
tegra_clk_ispb,
tegra_clk_kbc,
tegra_clk_kfuse,
tegra_clk_la,
tegra_clk_maud,
tegra_clk_mipi,
tegra_clk_mipibif,
tegra_clk_mipi_cal,
tegra_clk_mpe,
tegra_clk_mselect,
tegra_clk_msenc,
tegra_clk_ndflash,
tegra_clk_ndflash_8,
tegra_clk_ndspeed,
tegra_clk_ndspeed_8,
tegra_clk_nor,
tegra_clk_nvdec,
tegra_clk_nvenc,
tegra_clk_nvjpg,
tegra_clk_owr,
tegra_clk_owr_8,
tegra_clk_pcie,
tegra_clk_pclk,
tegra_clk_pll_a,
tegra_clk_pll_a_out0,
tegra_clk_pll_a1,
tegra_clk_pll_c,
tegra_clk_pll_c2,
tegra_clk_pll_c3,
tegra_clk_pll_c4,
tegra_clk_pll_c4_out0,
tegra_clk_pll_c4_out1,
tegra_clk_pll_c4_out2,
tegra_clk_pll_c4_out3,
tegra_clk_pll_c_out1,
tegra_clk_pll_d,
tegra_clk_pll_d2,
tegra_clk_pll_d2_out0,
tegra_clk_pll_d_out0,
tegra_clk_pll_dp,
tegra_clk_pll_e_out0,
tegra_clk_pll_g_ref,
tegra_clk_pll_m,
tegra_clk_pll_m_out1,
tegra_clk_pll_mb,
tegra_clk_pll_p,
tegra_clk_pll_p_out1,
tegra_clk_pll_p_out2,
tegra_clk_pll_p_out2_int,
tegra_clk_pll_p_out3,
tegra_clk_pll_p_out4,
tegra_clk_pll_p_out4_cpu,
tegra_clk_pll_p_out5,
tegra_clk_pll_p_out_hsio,
tegra_clk_pll_p_out_xusb,
tegra_clk_pll_p_out_cpu,
tegra_clk_pll_p_out_adsp,
tegra_clk_pll_ref,
tegra_clk_pll_re_out,
tegra_clk_pll_re_vco,
tegra_clk_pll_u,
tegra_clk_pll_u_out,
tegra_clk_pll_u_out1,
tegra_clk_pll_u_out2,
tegra_clk_pll_u_12m,
tegra_clk_pll_u_480m,
tegra_clk_pll_u_48m,
tegra_clk_pll_u_60m,
tegra_clk_pll_x,
tegra_clk_pll_x_out0,
tegra_clk_pwm,
tegra_clk_qspi,
tegra_clk_rtc,
tegra_clk_sata,
tegra_clk_sata_8,
tegra_clk_sata_cold,
tegra_clk_sata_oob,
tegra_clk_sata_oob_8,
tegra_clk_sbc1,
tegra_clk_sbc1_8,
tegra_clk_sbc1_9,
tegra_clk_sbc2,
tegra_clk_sbc2_8,
tegra_clk_sbc2_9,
tegra_clk_sbc3,
tegra_clk_sbc3_8,
tegra_clk_sbc3_9,
tegra_clk_sbc4,
tegra_clk_sbc4_8,
tegra_clk_sbc4_9,
tegra_clk_sbc5,
tegra_clk_sbc5_8,
tegra_clk_sbc6,
tegra_clk_sbc6_8,
tegra_clk_sclk,
tegra_clk_sdmmc_legacy,
tegra_clk_sdmmc1,
tegra_clk_sdmmc1_8,
tegra_clk_sdmmc1_9,
tegra_clk_sdmmc2,
tegra_clk_sdmmc2_8,
tegra_clk_sdmmc3,
tegra_clk_sdmmc3_8,
tegra_clk_sdmmc3_9,
tegra_clk_sdmmc4,
tegra_clk_sdmmc4_8,
tegra_clk_se,
tegra_clk_se_10,
tegra_clk_soc_therm,
tegra_clk_soc_therm_8,
tegra_clk_sor0,
tegra_clk_sor0_out,
tegra_clk_sor1,
tegra_clk_sor1_out,
tegra_clk_spdif,
tegra_clk_spdif_2x,
tegra_clk_spdif_in,
tegra_clk_spdif_in_8,
tegra_clk_spdif_in_sync,
tegra_clk_spdif_mux,
tegra_clk_spdif_out,
tegra_clk_timer,
tegra_clk_trace,
tegra_clk_tsec,
tegra_clk_tsec_8,
tegra_clk_tsecb,
tegra_clk_tsensor,
tegra_clk_tvdac,
tegra_clk_tvo,
tegra_clk_uarta,
tegra_clk_uarta_8,
tegra_clk_uartb,
tegra_clk_uartb_8,
tegra_clk_uartc,
tegra_clk_uartc_8,
tegra_clk_uartd,
tegra_clk_uartd_8,
tegra_clk_uarte,
tegra_clk_uarte_8,
tegra_clk_uartape,
tegra_clk_usb2,
tegra_clk_usb2_hsic_trk,
tegra_clk_usb2_trk,
tegra_clk_usb3,
tegra_clk_usbd,
tegra_clk_vcp,
tegra_clk_vde,
tegra_clk_vde_8,
tegra_clk_vfir,
tegra_clk_vi,
tegra_clk_vi_8,
tegra_clk_vi_9,
tegra_clk_vi_10,
tegra_clk_vi_i2c,
tegra_clk_vic03,
tegra_clk_vic03_8,
tegra_clk_vim2_clk,
tegra_clk_vimclk_sync,
tegra_clk_vi_sensor,
tegra_clk_vi_sensor_8,
tegra_clk_vi_sensor_9,
tegra_clk_vi_sensor2,
tegra_clk_vi_sensor2_8,
tegra_clk_xusb_dev,
tegra_clk_xusb_dev_src,
tegra_clk_xusb_dev_src_8,
tegra_clk_xusb_falcon_src,
tegra_clk_xusb_falcon_src_8,
tegra_clk_xusb_fs_src,
tegra_clk_xusb_gate,
tegra_clk_xusb_host,
tegra_clk_xusb_host_src,
tegra_clk_xusb_host_src_8,
tegra_clk_xusb_hs_src,
tegra_clk_xusb_hs_src_4,
tegra_clk_xusb_ss,
tegra_clk_xusb_ss_src,
tegra_clk_xusb_ss_src_8,
tegra_clk_xusb_ss_div2,
tegra_clk_xusb_ssp_src,
tegra_clk_sclk_mux,
tegra_clk_sor_safe,
tegra_clk_cec,
tegra_clk_ispa,
tegra_clk_dmic1,
tegra_clk_dmic2,
tegra_clk_dmic3,
tegra_clk_dmic1_sync_clk,
tegra_clk_dmic2_sync_clk,
tegra_clk_dmic3_sync_clk,
tegra_clk_dmic1_sync_clk_mux,
tegra_clk_dmic2_sync_clk_mux,
tegra_clk_dmic3_sync_clk_mux,
tegra_clk_iqc1,
tegra_clk_iqc2,
tegra_clk_pll_a_out_adsp,
tegra_clk_pll_a_out0_out_adsp,
tegra_clk_adsp,
tegra_clk_adsp_neon,
tegra_clk_max,
};
#endif /* _TEGRA_CLK_ID_H */
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