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https://github.com/edk2-porting/linux-next.git
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94aa44090e
Add missing 'static' qualifiers. Signed-off-by: Jonghwan Choi <jhbird.choi@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
267 lines
7.5 KiB
C
267 lines
7.5 KiB
C
/*
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* Copyright (c) 2010-2012 Samsung Electronics Co., Ltd.
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* http://www.samsung.com
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*
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* EXYNOS4X12 - CPU frequency scaling support
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <linux/err.h>
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#include <linux/clk.h>
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#include <linux/io.h>
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#include <linux/slab.h>
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#include <linux/cpufreq.h>
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#include <mach/regs-clock.h>
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#include <mach/cpufreq.h>
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static struct clk *cpu_clk;
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static struct clk *moutcore;
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static struct clk *mout_mpll;
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static struct clk *mout_apll;
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static unsigned int exynos4x12_volt_table[] = {
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1350000, 1287500, 1250000, 1187500, 1137500, 1087500, 1037500,
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1000000, 987500, 975000, 950000, 925000, 900000, 900000
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};
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static struct cpufreq_frequency_table exynos4x12_freq_table[] = {
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{L0, CPUFREQ_ENTRY_INVALID},
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{L1, 1400 * 1000},
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{L2, 1300 * 1000},
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{L3, 1200 * 1000},
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{L4, 1100 * 1000},
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{L5, 1000 * 1000},
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{L6, 900 * 1000},
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{L7, 800 * 1000},
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{L8, 700 * 1000},
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{L9, 600 * 1000},
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{L10, 500 * 1000},
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{L11, 400 * 1000},
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{L12, 300 * 1000},
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{L13, 200 * 1000},
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{0, CPUFREQ_TABLE_END},
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};
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static struct apll_freq *apll_freq_4x12;
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static struct apll_freq apll_freq_4212[] = {
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/*
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* values:
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* freq
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* clock divider for CORE, COREM0, COREM1, PERIPH, ATB, PCLK_DBG, APLL, CORE2
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* clock divider for COPY, HPM, RESERVED
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* PLL M, P, S
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*/
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APLL_FREQ(1500, 0, 3, 7, 0, 6, 1, 2, 0, 6, 2, 0, 250, 4, 0),
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APLL_FREQ(1400, 0, 3, 7, 0, 6, 1, 2, 0, 6, 2, 0, 175, 3, 0),
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APLL_FREQ(1300, 0, 3, 7, 0, 5, 1, 2, 0, 5, 2, 0, 325, 6, 0),
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APLL_FREQ(1200, 0, 3, 7, 0, 5, 1, 2, 0, 5, 2, 0, 200, 4, 0),
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APLL_FREQ(1100, 0, 3, 6, 0, 4, 1, 2, 0, 4, 2, 0, 275, 6, 0),
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APLL_FREQ(1000, 0, 2, 5, 0, 4, 1, 1, 0, 4, 2, 0, 125, 3, 0),
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APLL_FREQ(900, 0, 2, 5, 0, 3, 1, 1, 0, 3, 2, 0, 150, 4, 0),
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APLL_FREQ(800, 0, 2, 5, 0, 3, 1, 1, 0, 3, 2, 0, 100, 3, 0),
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APLL_FREQ(700, 0, 2, 4, 0, 3, 1, 1, 0, 3, 2, 0, 175, 3, 1),
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APLL_FREQ(600, 0, 2, 4, 0, 3, 1, 1, 0, 3, 2, 0, 200, 4, 1),
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APLL_FREQ(500, 0, 2, 4, 0, 3, 1, 1, 0, 3, 2, 0, 125, 3, 1),
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APLL_FREQ(400, 0, 2, 4, 0, 3, 1, 1, 0, 3, 2, 0, 100, 3, 1),
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APLL_FREQ(300, 0, 2, 4, 0, 2, 1, 1, 0, 3, 2, 0, 200, 4, 2),
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APLL_FREQ(200, 0, 1, 3, 0, 1, 1, 1, 0, 3, 2, 0, 100, 3, 2),
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};
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static struct apll_freq apll_freq_4412[] = {
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/*
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* values:
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* freq
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* clock divider for CORE, COREM0, COREM1, PERIPH, ATB, PCLK_DBG, APLL, CORE2
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* clock divider for COPY, HPM, CORES
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* PLL M, P, S
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*/
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APLL_FREQ(1500, 0, 3, 7, 0, 6, 1, 2, 0, 6, 0, 7, 250, 4, 0),
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APLL_FREQ(1400, 0, 3, 7, 0, 6, 1, 2, 0, 6, 0, 6, 175, 3, 0),
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APLL_FREQ(1300, 0, 3, 7, 0, 5, 1, 2, 0, 5, 0, 6, 325, 6, 0),
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APLL_FREQ(1200, 0, 3, 7, 0, 5, 1, 2, 0, 5, 0, 5, 200, 4, 0),
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APLL_FREQ(1100, 0, 3, 6, 0, 4, 1, 2, 0, 4, 0, 5, 275, 6, 0),
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APLL_FREQ(1000, 0, 2, 5, 0, 4, 1, 1, 0, 4, 0, 4, 125, 3, 0),
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APLL_FREQ(900, 0, 2, 5, 0, 3, 1, 1, 0, 3, 0, 4, 150, 4, 0),
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APLL_FREQ(800, 0, 2, 5, 0, 3, 1, 1, 0, 3, 0, 3, 100, 3, 0),
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APLL_FREQ(700, 0, 2, 4, 0, 3, 1, 1, 0, 3, 0, 3, 175, 3, 1),
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APLL_FREQ(600, 0, 2, 4, 0, 3, 1, 1, 0, 3, 0, 2, 200, 4, 1),
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APLL_FREQ(500, 0, 2, 4, 0, 3, 1, 1, 0, 3, 0, 2, 125, 3, 1),
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APLL_FREQ(400, 0, 2, 4, 0, 3, 1, 1, 0, 3, 0, 1, 100, 3, 1),
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APLL_FREQ(300, 0, 2, 4, 0, 2, 1, 1, 0, 3, 0, 1, 200, 4, 2),
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APLL_FREQ(200, 0, 1, 3, 0, 1, 1, 1, 0, 3, 0, 0, 100, 3, 2),
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};
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static void exynos4x12_set_clkdiv(unsigned int div_index)
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{
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unsigned int tmp;
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unsigned int stat_cpu1;
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/* Change Divider - CPU0 */
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tmp = apll_freq_4x12[div_index].clk_div_cpu0;
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__raw_writel(tmp, EXYNOS4_CLKDIV_CPU);
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while (__raw_readl(EXYNOS4_CLKDIV_STATCPU) & 0x11111111)
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cpu_relax();
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/* Change Divider - CPU1 */
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tmp = apll_freq_4x12[div_index].clk_div_cpu1;
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__raw_writel(tmp, EXYNOS4_CLKDIV_CPU1);
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if (soc_is_exynos4212())
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stat_cpu1 = 0x11;
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else
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stat_cpu1 = 0x111;
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while (__raw_readl(EXYNOS4_CLKDIV_STATCPU1) & stat_cpu1)
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cpu_relax();
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}
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static void exynos4x12_set_apll(unsigned int index)
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{
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unsigned int tmp, pdiv;
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/* 1. MUX_CORE_SEL = MPLL, ARMCLK uses MPLL for lock time */
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clk_set_parent(moutcore, mout_mpll);
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do {
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cpu_relax();
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tmp = (__raw_readl(EXYNOS4_CLKMUX_STATCPU)
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>> EXYNOS4_CLKSRC_CPU_MUXCORE_SHIFT);
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tmp &= 0x7;
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} while (tmp != 0x2);
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/* 2. Set APLL Lock time */
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pdiv = ((apll_freq_4x12[index].mps >> 8) & 0x3f);
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__raw_writel((pdiv * 250), EXYNOS4_APLL_LOCK);
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/* 3. Change PLL PMS values */
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tmp = __raw_readl(EXYNOS4_APLL_CON0);
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tmp &= ~((0x3ff << 16) | (0x3f << 8) | (0x7 << 0));
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tmp |= apll_freq_4x12[index].mps;
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__raw_writel(tmp, EXYNOS4_APLL_CON0);
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/* 4. wait_lock_time */
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do {
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cpu_relax();
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tmp = __raw_readl(EXYNOS4_APLL_CON0);
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} while (!(tmp & (0x1 << EXYNOS4_APLLCON0_LOCKED_SHIFT)));
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/* 5. MUX_CORE_SEL = APLL */
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clk_set_parent(moutcore, mout_apll);
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do {
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cpu_relax();
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tmp = __raw_readl(EXYNOS4_CLKMUX_STATCPU);
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tmp &= EXYNOS4_CLKMUX_STATCPU_MUXCORE_MASK;
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} while (tmp != (0x1 << EXYNOS4_CLKSRC_CPU_MUXCORE_SHIFT));
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}
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static bool exynos4x12_pms_change(unsigned int old_index, unsigned int new_index)
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{
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unsigned int old_pm = apll_freq_4x12[old_index].mps >> 8;
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unsigned int new_pm = apll_freq_4x12[new_index].mps >> 8;
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return (old_pm == new_pm) ? 0 : 1;
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}
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static void exynos4x12_set_frequency(unsigned int old_index,
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unsigned int new_index)
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{
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unsigned int tmp;
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if (old_index > new_index) {
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if (!exynos4x12_pms_change(old_index, new_index)) {
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/* 1. Change the system clock divider values */
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exynos4x12_set_clkdiv(new_index);
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/* 2. Change just s value in apll m,p,s value */
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tmp = __raw_readl(EXYNOS4_APLL_CON0);
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tmp &= ~(0x7 << 0);
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tmp |= apll_freq_4x12[new_index].mps & 0x7;
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__raw_writel(tmp, EXYNOS4_APLL_CON0);
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} else {
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/* Clock Configuration Procedure */
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/* 1. Change the system clock divider values */
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exynos4x12_set_clkdiv(new_index);
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/* 2. Change the apll m,p,s value */
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exynos4x12_set_apll(new_index);
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}
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} else if (old_index < new_index) {
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if (!exynos4x12_pms_change(old_index, new_index)) {
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/* 1. Change just s value in apll m,p,s value */
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tmp = __raw_readl(EXYNOS4_APLL_CON0);
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tmp &= ~(0x7 << 0);
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tmp |= apll_freq_4x12[new_index].mps & 0x7;
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__raw_writel(tmp, EXYNOS4_APLL_CON0);
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/* 2. Change the system clock divider values */
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exynos4x12_set_clkdiv(new_index);
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} else {
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/* Clock Configuration Procedure */
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/* 1. Change the apll m,p,s value */
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exynos4x12_set_apll(new_index);
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/* 2. Change the system clock divider values */
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exynos4x12_set_clkdiv(new_index);
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}
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}
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}
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int exynos4x12_cpufreq_init(struct exynos_dvfs_info *info)
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{
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unsigned long rate;
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cpu_clk = clk_get(NULL, "armclk");
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if (IS_ERR(cpu_clk))
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return PTR_ERR(cpu_clk);
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moutcore = clk_get(NULL, "moutcore");
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if (IS_ERR(moutcore))
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goto err_moutcore;
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mout_mpll = clk_get(NULL, "mout_mpll");
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if (IS_ERR(mout_mpll))
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goto err_mout_mpll;
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rate = clk_get_rate(mout_mpll) / 1000;
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mout_apll = clk_get(NULL, "mout_apll");
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if (IS_ERR(mout_apll))
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goto err_mout_apll;
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if (soc_is_exynos4212())
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apll_freq_4x12 = apll_freq_4212;
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else
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apll_freq_4x12 = apll_freq_4412;
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info->mpll_freq_khz = rate;
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/* 800Mhz */
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info->pll_safe_idx = L7;
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info->cpu_clk = cpu_clk;
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info->volt_table = exynos4x12_volt_table;
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info->freq_table = exynos4x12_freq_table;
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info->set_freq = exynos4x12_set_frequency;
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info->need_apll_change = exynos4x12_pms_change;
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return 0;
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err_mout_apll:
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clk_put(mout_mpll);
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err_mout_mpll:
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clk_put(moutcore);
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err_moutcore:
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clk_put(cpu_clk);
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pr_debug("%s: failed initialization\n", __func__);
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return -EINVAL;
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}
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EXPORT_SYMBOL(exynos4x12_cpufreq_init);
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