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5bf3df3f00
The remaining registers are separated into: - <mach/regs-ost.h> - <mach/regs-rtc.h> - <mach/regs-intc.h> and then we can remove pxa-regs.h completely. Instead of #include this file, let's: 1. include the specific <mach/regs-*.h> with care (if that's absolutely necessary) 2. define the registers in the driver, make cleanly defined API to expose the register access to external with sufficient reason Signed-off-by: Eric Miao <eric.miao@marvell.com>
379 lines
9.4 KiB
ArmAsm
379 lines
9.4 KiB
ArmAsm
/*
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* Low-level PXA250/210 sleep/wakeUp support
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*
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* Initial SA1110 code:
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* Copyright (c) 2001 Cliff Brake <cbrake@accelent.com>
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*
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* Adapted for PXA by Nicolas Pitre:
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* Copyright (c) 2002 Monta Vista Software, Inc.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License.
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*/
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#include <linux/linkage.h>
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#include <asm/assembler.h>
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#include <mach/hardware.h>
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#include <mach/pxa2xx-regs.h>
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#define MDREFR_KDIV 0x200a4000 // all banks
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#define CCCR_SLEEP 0x00000107 // L=7 2N=2 A=0 PPDIS=0 CPDIS=0
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.text
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pxa_cpu_save_cp:
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@ get coprocessor registers
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mrc p14, 0, r3, c6, c0, 0 @ clock configuration, for turbo mode
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mrc p15, 0, r4, c15, c1, 0 @ CP access reg
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mrc p15, 0, r5, c13, c0, 0 @ PID
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mrc p15, 0, r6, c3, c0, 0 @ domain ID
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mrc p15, 0, r7, c2, c0, 0 @ translation table base addr
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mrc p15, 0, r8, c1, c1, 0 @ auxiliary control reg
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mrc p15, 0, r9, c1, c0, 0 @ control reg
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bic r3, r3, #2 @ clear frequency change bit
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@ store them plus current virtual stack ptr on stack
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mov r10, sp
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stmfd sp!, {r3 - r10}
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mov pc, lr
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pxa_cpu_save_sp:
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@ preserve phys address of stack
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mov r0, sp
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str lr, [sp, #-4]!
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bl sleep_phys_sp
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ldr r1, =sleep_save_sp
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str r0, [r1]
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ldr pc, [sp], #4
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#ifdef CONFIG_PXA3xx
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/*
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* pxa3xx_cpu_suspend() - forces CPU into sleep state (S2D3C4)
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*
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* NOTE: unfortunately, pxa_cpu_save_cp can not be reused here since
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* the auxiliary control register address is different between pxa3xx
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* and pxa{25x,27x}
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*/
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ENTRY(pxa3xx_cpu_suspend)
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#ifndef CONFIG_IWMMXT
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mra r2, r3, acc0
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#endif
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stmfd sp!, {r2 - r12, lr} @ save registers on stack
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mrc p14, 0, r3, c6, c0, 0 @ clock configuration, for turbo mode
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mrc p15, 0, r4, c15, c1, 0 @ CP access reg
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mrc p15, 0, r5, c13, c0, 0 @ PID
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mrc p15, 0, r6, c3, c0, 0 @ domain ID
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mrc p15, 0, r7, c2, c0, 0 @ translation table base addr
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mrc p15, 0, r8, c1, c0, 1 @ auxiliary control reg
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mrc p15, 0, r9, c1, c0, 0 @ control reg
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bic r3, r3, #2 @ clear frequency change bit
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@ store them plus current virtual stack ptr on stack
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mov r10, sp
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stmfd sp!, {r3 - r10}
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@ store physical address of stack pointer
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mov r0, sp
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bl sleep_phys_sp
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ldr r1, =sleep_save_sp
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str r0, [r1]
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@ clean data cache
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bl xsc3_flush_kern_cache_all
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mov r0, #0x06 @ S2D3C4 mode
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mcr p14, 0, r0, c7, c0, 0 @ enter sleep
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20: b 20b @ waiting for sleep
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.data
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.align 5
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/*
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* pxa3xx_cpu_resume
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*/
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ENTRY(pxa3xx_cpu_resume)
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mov r0, #PSR_I_BIT | PSR_F_BIT | SVC_MODE @ set SVC, irqs off
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msr cpsr_c, r0
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ldr r0, sleep_save_sp @ stack phys addr
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ldmfd r0, {r3 - r9, sp} @ CP regs + virt stack ptr
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mov r1, #0
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mcr p15, 0, r1, c7, c7, 0 @ invalidate I & D caches, BTB
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mcr p15, 0, r1, c7, c10, 4 @ drain write (&fill) buffer
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mcr p15, 0, r1, c7, c5, 4 @ flush prefetch buffer
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mcr p15, 0, r1, c8, c7, 0 @ invalidate I & D TLBs
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mcr p14, 0, r3, c6, c0, 0 @ clock configuration, turbo mode.
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mcr p15, 0, r4, c15, c1, 0 @ CP access reg
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mcr p15, 0, r5, c13, c0, 0 @ PID
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mcr p15, 0, r6, c3, c0, 0 @ domain ID
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mcr p15, 0, r7, c2, c0, 0 @ translation table base addr
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mcr p15, 0, r8, c1, c0, 1 @ auxiliary control reg
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@ temporarily map resume_turn_on_mmu into the page table,
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@ otherwise prefetch abort occurs after MMU is turned on
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mov r1, r7
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bic r1, r1, #0x00ff
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bic r1, r1, #0x3f00
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ldr r2, =0x542e
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adr r3, resume_turn_on_mmu
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mov r3, r3, lsr #20
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orr r4, r2, r3, lsl #20
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ldr r5, [r1, r3, lsl #2]
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str r4, [r1, r3, lsl #2]
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@ Mapping page table address in the page table
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mov r6, r1, lsr #20
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orr r7, r2, r6, lsl #20
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ldr r8, [r1, r6, lsl #2]
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str r7, [r1, r6, lsl #2]
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ldr r2, =pxa3xx_resume_after_mmu @ absolute virtual address
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b resume_turn_on_mmu @ cache align execution
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.text
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pxa3xx_resume_after_mmu:
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/* restore the temporary mapping */
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str r5, [r1, r3, lsl #2]
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str r8, [r1, r6, lsl #2]
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b resume_after_mmu
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#endif /* CONFIG_PXA3xx */
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#ifdef CONFIG_PXA27x
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/*
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* pxa27x_cpu_suspend()
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*
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* Forces CPU into sleep state.
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*
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* r0 = value for PWRMODE M field for desired sleep state
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*/
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ENTRY(pxa27x_cpu_suspend)
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#ifndef CONFIG_IWMMXT
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mra r2, r3, acc0
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#endif
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stmfd sp!, {r2 - r12, lr} @ save registers on stack
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bl pxa_cpu_save_cp
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mov r5, r0 @ save sleep mode
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bl pxa_cpu_save_sp
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@ clean data cache
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bl xscale_flush_kern_cache_all
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@ Put the processor to sleep
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@ (also workaround for sighting 28071)
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@ prepare value for sleep mode
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mov r1, r5 @ sleep mode
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@ prepare pointer to physical address 0 (virtual mapping in generic.c)
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mov r2, #UNCACHED_PHYS_0
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@ prepare SDRAM refresh settings
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ldr r4, =MDREFR
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ldr r5, [r4]
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@ enable SDRAM self-refresh mode
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orr r5, r5, #MDREFR_SLFRSH
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@ set SDCLKx divide-by-2 bits (this is part of a workaround for Errata 50)
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ldr r6, =MDREFR_KDIV
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orr r5, r5, r6
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@ Intel PXA270 Specification Update notes problems sleeping
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@ with core operating above 91 MHz
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@ (see Errata 50, ...processor does not exit from sleep...)
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ldr r6, =CCCR
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ldr r8, [r6] @ keep original value for resume
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ldr r7, =CCCR_SLEEP @ prepare CCCR sleep value
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mov r0, #0x2 @ prepare value for CLKCFG
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@ align execution to a cache line
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b pxa_cpu_do_suspend
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#endif
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#ifdef CONFIG_PXA25x
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/*
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* pxa25x_cpu_suspend()
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*
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* Forces CPU into sleep state.
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*
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* r0 = value for PWRMODE M field for desired sleep state
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*/
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ENTRY(pxa25x_cpu_suspend)
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stmfd sp!, {r2 - r12, lr} @ save registers on stack
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bl pxa_cpu_save_cp
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mov r5, r0 @ save sleep mode
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bl pxa_cpu_save_sp
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@ clean data cache
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bl xscale_flush_kern_cache_all
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@ prepare value for sleep mode
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mov r1, r5 @ sleep mode
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@ prepare pointer to physical address 0 (virtual mapping in generic.c)
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mov r2, #UNCACHED_PHYS_0
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@ prepare SDRAM refresh settings
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ldr r4, =MDREFR
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ldr r5, [r4]
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@ enable SDRAM self-refresh mode
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orr r5, r5, #MDREFR_SLFRSH
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@ Intel PXA255 Specification Update notes problems
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@ about suspending with PXBus operating above 133MHz
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@ (see Errata 31, GPIO output signals, ... unpredictable in sleep
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@
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@ We keep the change-down close to the actual suspend on SDRAM
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@ as possible to eliminate messing about with the refresh clock
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@ as the system will restore with the original speed settings
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@
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@ Ben Dooks, 13-Sep-2004
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ldr r6, =CCCR
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ldr r8, [r6] @ keep original value for resume
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@ ensure x1 for run and turbo mode with memory clock
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bic r7, r8, #CCCR_M_MASK | CCCR_N_MASK
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orr r7, r7, #(1<<5) | (2<<7)
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@ check that the memory frequency is within limits
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and r14, r7, #CCCR_L_MASK
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teq r14, #1
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bicne r7, r7, #CCCR_L_MASK
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orrne r7, r7, #1 @@ 99.53MHz
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@ get ready for the change
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@ note, turbo is not preserved over sleep so there is no
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@ point in preserving it here. we save it on the stack with the
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@ other CP registers instead.
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mov r0, #0
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mcr p14, 0, r0, c6, c0, 0
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orr r0, r0, #2 @ initiate change bit
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b pxa_cpu_do_suspend
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#endif
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.ltorg
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.align 5
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pxa_cpu_do_suspend:
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@ All needed values are now in registers.
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@ These last instructions should be in cache
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@ initiate the frequency change...
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str r7, [r6]
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mcr p14, 0, r0, c6, c0, 0
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@ restore the original cpu speed value for resume
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str r8, [r6]
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@ need 6 13-MHz cycles before changing PWRMODE
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@ just set frequency to 91-MHz... 6*91/13 = 42
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mov r0, #42
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10: subs r0, r0, #1
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bne 10b
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@ Do not reorder...
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@ Intel PXA270 Specification Update notes problems performing
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@ external accesses after SDRAM is put in self-refresh mode
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@ (see Errata 39 ...hangs when entering self-refresh mode)
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@ force address lines low by reading at physical address 0
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ldr r3, [r2]
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@ put SDRAM into self-refresh
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str r5, [r4]
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@ enter sleep mode
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mcr p14, 0, r1, c7, c0, 0 @ PWRMODE
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20: b 20b @ loop waiting for sleep
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/*
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* pxa_cpu_resume()
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*
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* entry point from bootloader into kernel during resume
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*
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* Note: Yes, part of the following code is located into the .data section.
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* This is to allow sleep_save_sp to be accessed with a relative load
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* while we can't rely on any MMU translation. We could have put
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* sleep_save_sp in the .text section as well, but some setups might
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* insist on it to be truly read-only.
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*/
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.data
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.align 5
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ENTRY(pxa_cpu_resume)
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mov r0, #PSR_I_BIT | PSR_F_BIT | SVC_MODE @ set SVC, irqs off
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msr cpsr_c, r0
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ldr r0, sleep_save_sp @ stack phys addr
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ldr r2, =resume_after_mmu @ its absolute virtual address
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ldmfd r0, {r3 - r9, sp} @ CP regs + virt stack ptr
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mov r1, #0
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mcr p15, 0, r1, c8, c7, 0 @ invalidate I & D TLBs
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mcr p15, 0, r1, c7, c7, 0 @ invalidate I & D caches, BTB
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#ifdef CONFIG_XSCALE_CACHE_ERRATA
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bic r9, r9, #0x0004 @ see cpu_xscale_proc_init
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#endif
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mcr p14, 0, r3, c6, c0, 0 @ clock configuration, turbo mode.
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mcr p15, 0, r4, c15, c1, 0 @ CP access reg
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mcr p15, 0, r5, c13, c0, 0 @ PID
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mcr p15, 0, r6, c3, c0, 0 @ domain ID
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mcr p15, 0, r7, c2, c0, 0 @ translation table base addr
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mcr p15, 0, r8, c1, c1, 0 @ auxiliary control reg
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b resume_turn_on_mmu @ cache align execution
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.align 5
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resume_turn_on_mmu:
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mcr p15, 0, r9, c1, c0, 0 @ turn on MMU, caches, etc.
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@ Let us ensure we jump to resume_after_mmu only when the mcr above
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@ actually took effect. They call it the "cpwait" operation.
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mrc p15, 0, r1, c2, c0, 0 @ queue a dependency on CP15
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sub pc, r2, r1, lsr #32 @ jump to virtual addr
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nop
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nop
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nop
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sleep_save_sp:
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.word 0 @ preserve stack phys ptr here
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.text
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resume_after_mmu:
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#ifdef CONFIG_XSCALE_CACHE_ERRATA
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bl cpu_xscale_proc_init
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#endif
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ldmfd sp!, {r2, r3}
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#ifndef CONFIG_IWMMXT
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mar acc0, r2, r3
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#endif
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ldmfd sp!, {r4 - r12, pc} @ return to caller
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