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0f4f0672ac
To add support for perf events and to allow the hardware counters to be shared with oprofile, we need a way to reserve access to the pmu (performance monitor unit). Platforms with PMU interrupts should register the interrupts in arch/arm/kernel/pmu.c Signed-off-by: Jamie Iles <jamie.iles@picochip.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
76 lines
1.7 KiB
C
76 lines
1.7 KiB
C
/*
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* linux/arch/arm/include/asm/pmu.h
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*
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* Copyright (C) 2009 picoChip Designs Ltd, Jamie Iles
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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*/
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#ifndef __ARM_PMU_H__
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#define __ARM_PMU_H__
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#ifdef CONFIG_CPU_HAS_PMU
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struct pmu_irqs {
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const int *irqs;
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int num_irqs;
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};
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/**
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* reserve_pmu() - reserve the hardware performance counters
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*
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* Reserve the hardware performance counters in the system for exclusive use.
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* The 'struct pmu_irqs' for the system is returned on success, ERR_PTR()
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* encoded error on failure.
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*/
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extern const struct pmu_irqs *
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reserve_pmu(void);
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/**
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* release_pmu() - Relinquish control of the performance counters
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*
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* Release the performance counters and allow someone else to use them.
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* Callers must have disabled the counters and released IRQs before calling
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* this. The 'struct pmu_irqs' returned from reserve_pmu() must be passed as
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* a cookie.
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*/
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extern int
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release_pmu(const struct pmu_irqs *irqs);
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/**
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* init_pmu() - Initialise the PMU.
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*
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* Initialise the system ready for PMU enabling. This should typically set the
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* IRQ affinity and nothing else. The users (oprofile/perf events etc) will do
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* the actual hardware initialisation.
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*/
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extern int
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init_pmu(void);
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#else /* CONFIG_CPU_HAS_PMU */
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static inline const struct pmu_irqs *
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reserve_pmu(void)
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{
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return ERR_PTR(-ENODEV);
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}
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static inline int
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release_pmu(const struct pmu_irqs *irqs)
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{
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return -ENODEV;
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}
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static inline int
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init_pmu(void)
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{
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return -ENODEV;
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}
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#endif /* CONFIG_CPU_HAS_PMU */
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#endif /* __ARM_PMU_H__ */
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