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52168e60f7
This reverts commite51af66308, which was wrongly hoovered up and submitted about a month after a better fix had already been merged. The better fix is commitcbda1ba898("PCI/iommu: blacklist DMAR on Intel G31/G33 chipsets"), where we do this blacklisting based on the DMI identification for the offending motherboard, since sometimes this chipset (or at least a chipset with the same PCI ID) apparently _does_ actually have an IOMMU. Signed-off-by: David Woodhouse <David.Woodhouse@intel.com> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
283 lines
7.0 KiB
C
283 lines
7.0 KiB
C
/* Various workarounds for chipset bugs.
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This code runs very early and can't use the regular PCI subsystem
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The entries are keyed to PCI bridges which usually identify chipsets
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uniquely.
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This is only for whole classes of chipsets with specific problems which
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need early invasive action (e.g. before the timers are initialized).
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Most PCI device specific workarounds can be done later and should be
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in standard PCI quirks
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Mainboard specific bugs should be handled by DMI entries.
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CPU specific bugs in setup.c */
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#include <linux/pci.h>
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#include <linux/acpi.h>
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#include <linux/pci_ids.h>
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#include <asm/pci-direct.h>
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#include <asm/dma.h>
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#include <asm/io_apic.h>
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#include <asm/apic.h>
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#include <asm/iommu.h>
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static void __init fix_hypertransport_config(int num, int slot, int func)
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{
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u32 htcfg;
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/*
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* we found a hypertransport bus
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* make sure that we are broadcasting
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* interrupts to all cpus on the ht bus
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* if we're using extended apic ids
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*/
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htcfg = read_pci_config(num, slot, func, 0x68);
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if (htcfg & (1 << 18)) {
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printk(KERN_INFO "Detected use of extended apic ids "
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"on hypertransport bus\n");
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if ((htcfg & (1 << 17)) == 0) {
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printk(KERN_INFO "Enabling hypertransport extended "
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"apic interrupt broadcast\n");
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printk(KERN_INFO "Note this is a bios bug, "
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"please contact your hw vendor\n");
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htcfg |= (1 << 17);
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write_pci_config(num, slot, func, 0x68, htcfg);
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}
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}
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}
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static void __init via_bugs(int num, int slot, int func)
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{
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#ifdef CONFIG_GART_IOMMU
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if ((max_pfn > MAX_DMA32_PFN || force_iommu) &&
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!gart_iommu_aperture_allowed) {
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printk(KERN_INFO
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"Looks like a VIA chipset. Disabling IOMMU."
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" Override with iommu=allowed\n");
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gart_iommu_aperture_disabled = 1;
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}
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#endif
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}
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#ifdef CONFIG_ACPI
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#ifdef CONFIG_X86_IO_APIC
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static int __init nvidia_hpet_check(struct acpi_table_header *header)
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{
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return 0;
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}
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#endif /* CONFIG_X86_IO_APIC */
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#endif /* CONFIG_ACPI */
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static void __init nvidia_bugs(int num, int slot, int func)
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{
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#ifdef CONFIG_ACPI
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#ifdef CONFIG_X86_IO_APIC
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/*
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* All timer overrides on Nvidia are
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* wrong unless HPET is enabled.
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* Unfortunately that's not true on many Asus boards.
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* We don't know yet how to detect this automatically, but
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* at least allow a command line override.
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*/
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if (acpi_use_timer_override)
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return;
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if (acpi_table_parse(ACPI_SIG_HPET, nvidia_hpet_check)) {
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acpi_skip_timer_override = 1;
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printk(KERN_INFO "Nvidia board "
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"detected. Ignoring ACPI "
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"timer override.\n");
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printk(KERN_INFO "If you got timer trouble "
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"try acpi_use_timer_override\n");
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}
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#endif
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#endif
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/* RED-PEN skip them on mptables too? */
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}
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#if defined(CONFIG_ACPI) && defined(CONFIG_X86_IO_APIC)
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static u32 __init ati_ixp4x0_rev(int num, int slot, int func)
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{
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u32 d;
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u8 b;
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b = read_pci_config_byte(num, slot, func, 0xac);
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b &= ~(1<<5);
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write_pci_config_byte(num, slot, func, 0xac, b);
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d = read_pci_config(num, slot, func, 0x70);
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d |= 1<<8;
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write_pci_config(num, slot, func, 0x70, d);
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d = read_pci_config(num, slot, func, 0x8);
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d &= 0xff;
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return d;
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}
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static void __init ati_bugs(int num, int slot, int func)
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{
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u32 d;
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u8 b;
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if (acpi_use_timer_override)
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return;
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d = ati_ixp4x0_rev(num, slot, func);
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if (d < 0x82)
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acpi_skip_timer_override = 1;
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else {
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/* check for IRQ0 interrupt swap */
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outb(0x72, 0xcd6); b = inb(0xcd7);
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if (!(b & 0x2))
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acpi_skip_timer_override = 1;
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}
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if (acpi_skip_timer_override) {
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printk(KERN_INFO "SB4X0 revision 0x%x\n", d);
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printk(KERN_INFO "Ignoring ACPI timer override.\n");
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printk(KERN_INFO "If you got timer trouble "
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"try acpi_use_timer_override\n");
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}
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}
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static u32 __init ati_sbx00_rev(int num, int slot, int func)
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{
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u32 old, d;
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d = read_pci_config(num, slot, func, 0x70);
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old = d;
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d &= ~(1<<8);
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write_pci_config(num, slot, func, 0x70, d);
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d = read_pci_config(num, slot, func, 0x8);
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d &= 0xff;
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write_pci_config(num, slot, func, 0x70, old);
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return d;
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}
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static void __init ati_bugs_contd(int num, int slot, int func)
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{
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u32 d, rev;
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if (acpi_use_timer_override)
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return;
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rev = ati_sbx00_rev(num, slot, func);
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if (rev > 0x13)
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return;
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/* check for IRQ0 interrupt swap */
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d = read_pci_config(num, slot, func, 0x64);
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if (!(d & (1<<14)))
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acpi_skip_timer_override = 1;
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if (acpi_skip_timer_override) {
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printk(KERN_INFO "SB600 revision 0x%x\n", rev);
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printk(KERN_INFO "Ignoring ACPI timer override.\n");
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printk(KERN_INFO "If you got timer trouble "
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"try acpi_use_timer_override\n");
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}
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}
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#else
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static void __init ati_bugs(int num, int slot, int func)
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{
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}
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static void __init ati_bugs_contd(int num, int slot, int func)
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{
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}
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#endif
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#define QFLAG_APPLY_ONCE 0x1
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#define QFLAG_APPLIED 0x2
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#define QFLAG_DONE (QFLAG_APPLY_ONCE|QFLAG_APPLIED)
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struct chipset {
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u32 vendor;
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u32 device;
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u32 class;
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u32 class_mask;
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u32 flags;
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void (*f)(int num, int slot, int func);
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};
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static struct chipset early_qrk[] __initdata = {
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{ PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID,
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PCI_CLASS_BRIDGE_PCI, PCI_ANY_ID, QFLAG_APPLY_ONCE, nvidia_bugs },
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{ PCI_VENDOR_ID_VIA, PCI_ANY_ID,
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PCI_CLASS_BRIDGE_PCI, PCI_ANY_ID, QFLAG_APPLY_ONCE, via_bugs },
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{ PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_K8_NB,
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PCI_CLASS_BRIDGE_HOST, PCI_ANY_ID, 0, fix_hypertransport_config },
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{ PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP400_SMBUS,
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PCI_CLASS_SERIAL_SMBUS, PCI_ANY_ID, 0, ati_bugs },
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{ PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SBX00_SMBUS,
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PCI_CLASS_SERIAL_SMBUS, PCI_ANY_ID, 0, ati_bugs_contd },
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{}
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};
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/**
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* check_dev_quirk - apply early quirks to a given PCI device
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* @num: bus number
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* @slot: slot number
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* @func: PCI function
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*
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* Check the vendor & device ID against the early quirks table.
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*
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* If the device is single function, let early_quirks() know so we don't
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* poke at this device again.
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*/
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static int __init check_dev_quirk(int num, int slot, int func)
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{
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u16 class;
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u16 vendor;
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u16 device;
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u8 type;
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int i;
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class = read_pci_config_16(num, slot, func, PCI_CLASS_DEVICE);
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if (class == 0xffff)
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return -1; /* no class, treat as single function */
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vendor = read_pci_config_16(num, slot, func, PCI_VENDOR_ID);
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device = read_pci_config_16(num, slot, func, PCI_DEVICE_ID);
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for (i = 0; early_qrk[i].f != NULL; i++) {
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if (((early_qrk[i].vendor == PCI_ANY_ID) ||
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(early_qrk[i].vendor == vendor)) &&
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((early_qrk[i].device == PCI_ANY_ID) ||
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(early_qrk[i].device == device)) &&
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(!((early_qrk[i].class ^ class) &
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early_qrk[i].class_mask))) {
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if ((early_qrk[i].flags &
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QFLAG_DONE) != QFLAG_DONE)
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early_qrk[i].f(num, slot, func);
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early_qrk[i].flags |= QFLAG_APPLIED;
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}
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}
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type = read_pci_config_byte(num, slot, func,
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PCI_HEADER_TYPE);
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if (!(type & 0x80))
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return -1;
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return 0;
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}
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void __init early_quirks(void)
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{
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int num, slot, func;
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if (!early_pci_allowed())
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return;
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/* Poor man's PCI discovery */
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for (num = 0; num < 32; num++)
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for (slot = 0; slot < 32; slot++)
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for (func = 0; func < 8; func++) {
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/* Only probe function 0 on single fn devices */
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if (check_dev_quirk(num, slot, func))
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break;
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}
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}
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