mirror of
https://github.com/edk2-porting/linux-next.git
synced 2024-12-28 15:13:55 +08:00
745d8ae462
Spoofcheck can't be enabled if VF MAC is zero.
Vice versa, can't zero MAC if spoofcheck is on.
Fixes: 8f7ba3ca12 ('net/mlx4: Add set VF mac address support')
Signed-off-by: Eugenia Emantayev <eugenia@mellanox.com>
Signed-off-by: Tariq Toukan <tariqt@mellanox.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
335 lines
9.9 KiB
C
335 lines
9.9 KiB
C
/*
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* Copyright (c) 2006 Cisco Systems, Inc. All rights reserved.
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*
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* This software is available to you under a choice of one of two
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* licenses. You may choose to be licensed under the terms of the GNU
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* General Public License (GPL) Version 2, available from the file
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* COPYING in the main directory of this source tree, or the
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* OpenIB.org BSD license below:
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*
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* Redistribution and use in source and binary forms, with or
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* without modification, are permitted provided that the following
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* conditions are met:
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*
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* - Redistributions of source code must retain the above
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* copyright notice, this list of conditions and the following
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* disclaimer.
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*
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* - Redistributions in binary form must reproduce the above
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* copyright notice, this list of conditions and the following
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* disclaimer in the documentation and/or other materials
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* provided with the distribution.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
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* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*/
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#ifndef MLX4_CMD_H
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#define MLX4_CMD_H
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#include <linux/dma-mapping.h>
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#include <linux/if_link.h>
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#include <linux/mlx4/device.h>
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#include <linux/netdevice.h>
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enum {
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/* initialization and general commands */
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MLX4_CMD_SYS_EN = 0x1,
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MLX4_CMD_SYS_DIS = 0x2,
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MLX4_CMD_MAP_FA = 0xfff,
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MLX4_CMD_UNMAP_FA = 0xffe,
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MLX4_CMD_RUN_FW = 0xff6,
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MLX4_CMD_MOD_STAT_CFG = 0x34,
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MLX4_CMD_QUERY_DEV_CAP = 0x3,
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MLX4_CMD_QUERY_FW = 0x4,
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MLX4_CMD_ENABLE_LAM = 0xff8,
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MLX4_CMD_DISABLE_LAM = 0xff7,
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MLX4_CMD_QUERY_DDR = 0x5,
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MLX4_CMD_QUERY_ADAPTER = 0x6,
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MLX4_CMD_INIT_HCA = 0x7,
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MLX4_CMD_CLOSE_HCA = 0x8,
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MLX4_CMD_INIT_PORT = 0x9,
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MLX4_CMD_CLOSE_PORT = 0xa,
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MLX4_CMD_QUERY_HCA = 0xb,
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MLX4_CMD_QUERY_PORT = 0x43,
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MLX4_CMD_SENSE_PORT = 0x4d,
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MLX4_CMD_HW_HEALTH_CHECK = 0x50,
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MLX4_CMD_SET_PORT = 0xc,
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MLX4_CMD_SET_NODE = 0x5a,
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MLX4_CMD_QUERY_FUNC = 0x56,
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MLX4_CMD_ACCESS_DDR = 0x2e,
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MLX4_CMD_MAP_ICM = 0xffa,
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MLX4_CMD_UNMAP_ICM = 0xff9,
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MLX4_CMD_MAP_ICM_AUX = 0xffc,
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MLX4_CMD_UNMAP_ICM_AUX = 0xffb,
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MLX4_CMD_SET_ICM_SIZE = 0xffd,
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MLX4_CMD_ACCESS_REG = 0x3b,
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MLX4_CMD_ALLOCATE_VPP = 0x80,
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MLX4_CMD_SET_VPORT_QOS = 0x81,
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/*master notify fw on finish for slave's flr*/
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MLX4_CMD_INFORM_FLR_DONE = 0x5b,
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MLX4_CMD_VIRT_PORT_MAP = 0x5c,
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MLX4_CMD_GET_OP_REQ = 0x59,
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/* TPT commands */
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MLX4_CMD_SW2HW_MPT = 0xd,
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MLX4_CMD_QUERY_MPT = 0xe,
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MLX4_CMD_HW2SW_MPT = 0xf,
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MLX4_CMD_READ_MTT = 0x10,
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MLX4_CMD_WRITE_MTT = 0x11,
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MLX4_CMD_SYNC_TPT = 0x2f,
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/* EQ commands */
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MLX4_CMD_MAP_EQ = 0x12,
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MLX4_CMD_SW2HW_EQ = 0x13,
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MLX4_CMD_HW2SW_EQ = 0x14,
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MLX4_CMD_QUERY_EQ = 0x15,
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/* CQ commands */
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MLX4_CMD_SW2HW_CQ = 0x16,
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MLX4_CMD_HW2SW_CQ = 0x17,
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MLX4_CMD_QUERY_CQ = 0x18,
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MLX4_CMD_MODIFY_CQ = 0x2c,
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/* SRQ commands */
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MLX4_CMD_SW2HW_SRQ = 0x35,
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MLX4_CMD_HW2SW_SRQ = 0x36,
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MLX4_CMD_QUERY_SRQ = 0x37,
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MLX4_CMD_ARM_SRQ = 0x40,
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/* QP/EE commands */
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MLX4_CMD_RST2INIT_QP = 0x19,
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MLX4_CMD_INIT2RTR_QP = 0x1a,
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MLX4_CMD_RTR2RTS_QP = 0x1b,
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MLX4_CMD_RTS2RTS_QP = 0x1c,
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MLX4_CMD_SQERR2RTS_QP = 0x1d,
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MLX4_CMD_2ERR_QP = 0x1e,
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MLX4_CMD_RTS2SQD_QP = 0x1f,
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MLX4_CMD_SQD2SQD_QP = 0x38,
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MLX4_CMD_SQD2RTS_QP = 0x20,
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MLX4_CMD_2RST_QP = 0x21,
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MLX4_CMD_QUERY_QP = 0x22,
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MLX4_CMD_INIT2INIT_QP = 0x2d,
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MLX4_CMD_SUSPEND_QP = 0x32,
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MLX4_CMD_UNSUSPEND_QP = 0x33,
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MLX4_CMD_UPDATE_QP = 0x61,
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/* special QP and management commands */
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MLX4_CMD_CONF_SPECIAL_QP = 0x23,
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MLX4_CMD_MAD_IFC = 0x24,
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MLX4_CMD_MAD_DEMUX = 0x203,
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/* multicast commands */
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MLX4_CMD_READ_MCG = 0x25,
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MLX4_CMD_WRITE_MCG = 0x26,
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MLX4_CMD_MGID_HASH = 0x27,
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/* miscellaneous commands */
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MLX4_CMD_DIAG_RPRT = 0x30,
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MLX4_CMD_NOP = 0x31,
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MLX4_CMD_CONFIG_DEV = 0x3a,
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MLX4_CMD_ACCESS_MEM = 0x2e,
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MLX4_CMD_SET_VEP = 0x52,
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/* Ethernet specific commands */
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MLX4_CMD_SET_VLAN_FLTR = 0x47,
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MLX4_CMD_SET_MCAST_FLTR = 0x48,
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MLX4_CMD_DUMP_ETH_STATS = 0x49,
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/* Communication channel commands */
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MLX4_CMD_ARM_COMM_CHANNEL = 0x57,
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MLX4_CMD_GEN_EQE = 0x58,
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/* virtual commands */
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MLX4_CMD_ALLOC_RES = 0xf00,
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MLX4_CMD_FREE_RES = 0xf01,
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MLX4_CMD_MCAST_ATTACH = 0xf05,
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MLX4_CMD_UCAST_ATTACH = 0xf06,
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MLX4_CMD_PROMISC = 0xf08,
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MLX4_CMD_QUERY_FUNC_CAP = 0xf0a,
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MLX4_CMD_QP_ATTACH = 0xf0b,
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/* debug commands */
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MLX4_CMD_QUERY_DEBUG_MSG = 0x2a,
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MLX4_CMD_SET_DEBUG_MSG = 0x2b,
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/* statistics commands */
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MLX4_CMD_QUERY_IF_STAT = 0X54,
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MLX4_CMD_SET_IF_STAT = 0X55,
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/* register/delete flow steering network rules */
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MLX4_QP_FLOW_STEERING_ATTACH = 0x65,
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MLX4_QP_FLOW_STEERING_DETACH = 0x66,
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MLX4_FLOW_STEERING_IB_UC_QP_RANGE = 0x64,
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/* Update and read QCN parameters */
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MLX4_CMD_CONGESTION_CTRL_OPCODE = 0x68,
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};
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enum {
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MLX4_CMD_TIME_CLASS_A = 60000,
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MLX4_CMD_TIME_CLASS_B = 60000,
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MLX4_CMD_TIME_CLASS_C = 60000,
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};
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enum {
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/* virtual to physical port mapping opcode modifiers */
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MLX4_GET_PORT_VIRT2PHY = 0x0,
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MLX4_SET_PORT_VIRT2PHY = 0x1,
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};
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enum {
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MLX4_MAILBOX_SIZE = 4096,
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MLX4_ACCESS_MEM_ALIGN = 256,
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};
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enum {
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/* Set port opcode modifiers */
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MLX4_SET_PORT_IB_OPCODE = 0x0,
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MLX4_SET_PORT_ETH_OPCODE = 0x1,
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MLX4_SET_PORT_BEACON_OPCODE = 0x4,
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};
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enum {
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/* Set port Ethernet input modifiers */
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MLX4_SET_PORT_GENERAL = 0x0,
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MLX4_SET_PORT_RQP_CALC = 0x1,
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MLX4_SET_PORT_MAC_TABLE = 0x2,
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MLX4_SET_PORT_VLAN_TABLE = 0x3,
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MLX4_SET_PORT_PRIO_MAP = 0x4,
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MLX4_SET_PORT_GID_TABLE = 0x5,
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MLX4_SET_PORT_PRIO2TC = 0x8,
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MLX4_SET_PORT_SCHEDULER = 0x9,
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MLX4_SET_PORT_VXLAN = 0xB,
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MLX4_SET_PORT_ROCE_ADDR = 0xD
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};
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enum {
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MLX4_CMD_MAD_DEMUX_CONFIG = 0,
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MLX4_CMD_MAD_DEMUX_QUERY_STATE = 1,
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MLX4_CMD_MAD_DEMUX_QUERY_RESTR = 2, /* Query mad demux restrictions */
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};
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enum {
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MLX4_CMD_WRAPPED,
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MLX4_CMD_NATIVE
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};
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/*
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* MLX4_RX_CSUM_MODE_VAL_NON_TCP_UDP -
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* Receive checksum value is reported in CQE also for non TCP/UDP packets.
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*
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* MLX4_RX_CSUM_MODE_L4 -
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* L4_CSUM bit in CQE, which indicates whether or not L4 checksum
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* was validated correctly, is supported.
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*
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* MLX4_RX_CSUM_MODE_IP_OK_IP_NON_TCP_UDP -
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* IP_OK CQE's field is supported also for non TCP/UDP IP packets.
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*
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* MLX4_RX_CSUM_MODE_MULTI_VLAN -
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* Receive Checksum offload is supported for packets with more than 2 vlan headers.
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*/
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enum mlx4_rx_csum_mode {
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MLX4_RX_CSUM_MODE_VAL_NON_TCP_UDP = 1UL << 0,
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MLX4_RX_CSUM_MODE_L4 = 1UL << 1,
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MLX4_RX_CSUM_MODE_IP_OK_IP_NON_TCP_UDP = 1UL << 2,
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MLX4_RX_CSUM_MODE_MULTI_VLAN = 1UL << 3
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};
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struct mlx4_config_dev_params {
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u16 vxlan_udp_dport;
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u8 rx_csum_flags_port_1;
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u8 rx_csum_flags_port_2;
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};
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enum mlx4_en_congestion_control_algorithm {
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MLX4_CTRL_ALGO_802_1_QAU_REACTION_POINT = 0,
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};
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enum mlx4_en_congestion_control_opmod {
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MLX4_CONGESTION_CONTROL_GET_PARAMS,
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MLX4_CONGESTION_CONTROL_GET_STATISTICS,
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MLX4_CONGESTION_CONTROL_SET_PARAMS = 4,
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};
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struct mlx4_dev;
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struct mlx4_cmd_mailbox {
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void *buf;
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dma_addr_t dma;
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};
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int __mlx4_cmd(struct mlx4_dev *dev, u64 in_param, u64 *out_param,
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int out_is_imm, u32 in_modifier, u8 op_modifier,
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u16 op, unsigned long timeout, int native);
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/* Invoke a command with no output parameter */
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static inline int mlx4_cmd(struct mlx4_dev *dev, u64 in_param, u32 in_modifier,
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u8 op_modifier, u16 op, unsigned long timeout,
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int native)
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{
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return __mlx4_cmd(dev, in_param, NULL, 0, in_modifier,
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op_modifier, op, timeout, native);
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}
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/* Invoke a command with an output mailbox */
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static inline int mlx4_cmd_box(struct mlx4_dev *dev, u64 in_param, u64 out_param,
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u32 in_modifier, u8 op_modifier, u16 op,
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unsigned long timeout, int native)
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{
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return __mlx4_cmd(dev, in_param, &out_param, 0, in_modifier,
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op_modifier, op, timeout, native);
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}
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/*
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* Invoke a command with an immediate output parameter (and copy the
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* output into the caller's out_param pointer after the command
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* executes).
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*/
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static inline int mlx4_cmd_imm(struct mlx4_dev *dev, u64 in_param, u64 *out_param,
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u32 in_modifier, u8 op_modifier, u16 op,
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unsigned long timeout, int native)
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{
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return __mlx4_cmd(dev, in_param, out_param, 1, in_modifier,
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op_modifier, op, timeout, native);
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}
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struct mlx4_cmd_mailbox *mlx4_alloc_cmd_mailbox(struct mlx4_dev *dev);
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void mlx4_free_cmd_mailbox(struct mlx4_dev *dev, struct mlx4_cmd_mailbox *mailbox);
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int mlx4_get_counter_stats(struct mlx4_dev *dev, int counter_index,
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struct mlx4_counter *counter_stats, int reset);
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int mlx4_get_vf_stats(struct mlx4_dev *dev, int port, int vf_idx,
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struct ifla_vf_stats *vf_stats);
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u32 mlx4_comm_get_version(void);
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int mlx4_set_vf_mac(struct mlx4_dev *dev, int port, int vf, u8 *mac);
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int mlx4_set_vf_vlan(struct mlx4_dev *dev, int port, int vf, u16 vlan,
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u8 qos, __be16 proto);
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int mlx4_set_vf_rate(struct mlx4_dev *dev, int port, int vf, int min_tx_rate,
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int max_tx_rate);
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int mlx4_set_vf_spoofchk(struct mlx4_dev *dev, int port, int vf, bool setting);
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int mlx4_get_vf_config(struct mlx4_dev *dev, int port, int vf, struct ifla_vf_info *ivf);
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int mlx4_set_vf_link_state(struct mlx4_dev *dev, int port, int vf, int link_state);
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int mlx4_config_dev_retrieval(struct mlx4_dev *dev,
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struct mlx4_config_dev_params *params);
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void mlx4_cmd_wake_completions(struct mlx4_dev *dev);
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void mlx4_report_internal_err_comm_event(struct mlx4_dev *dev);
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/*
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* mlx4_get_slave_default_vlan -
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* return true if VST ( default vlan)
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* if VST, will return vlan & qos (if not NULL)
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*/
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bool mlx4_get_slave_default_vlan(struct mlx4_dev *dev, int port, int slave,
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u16 *vlan, u8 *qos);
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#define MLX4_COMM_GET_IF_REV(cmd_chan_ver) (u8)((cmd_chan_ver) >> 8)
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#define COMM_CHAN_EVENT_INTERNAL_ERR (1 << 17)
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#endif /* MLX4_CMD_H */
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