mirror of
https://github.com/edk2-porting/linux-next.git
synced 2025-01-08 21:53:54 +08:00
5c6366e14d
In OMAP3xxx DISPC_DIVISOR register has a logical clock divisor (lcd_div) field. The lcd_div is common, for deciding the DISPC core functional clock frequency, and the final pixel clock frequency for LCD display. In OMAP4, there are 2 LCD channels, hence two divisor registers, DISPC_DIVISOR1 and DISPC_DIVISOR2. Also, there is a third register DISPC_DIVISOR. The DISPC_DIVISOR in OMAP4 is used to configure lcd_div exclusively for core functional clock configuration. For pixel clock configuration of primary and secondary LCDs, lcd_div of DISPC_DIVISOR1 and DISPC_DIVISOR2 are used respectively Signed-off-by: Archit Taneja <archit@ti.com> Signed-off-by: Raghuveer Murthy <raghuveer.murthy@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
68 lines
2.1 KiB
C
68 lines
2.1 KiB
C
/*
|
|
* linux/drivers/video/omap2/dss/dss_features.h
|
|
*
|
|
* Copyright (C) 2010 Texas Instruments
|
|
* Author: Archit Taneja <archit@ti.com>
|
|
*
|
|
* This program is free software; you can redistribute it and/or modify it
|
|
* under the terms of the GNU General Public License version 2 as published by
|
|
* the Free Software Foundation.
|
|
*
|
|
* This program is distributed in the hope that it will be useful, but WITHOUT
|
|
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
|
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
|
* more details.
|
|
*
|
|
* You should have received a copy of the GNU General Public License along with
|
|
* this program. If not, see <http://www.gnu.org/licenses/>.
|
|
*/
|
|
|
|
#ifndef __OMAP2_DSS_FEATURES_H
|
|
#define __OMAP2_DSS_FEATURES_H
|
|
|
|
#define MAX_DSS_MANAGERS 3
|
|
#define MAX_DSS_OVERLAYS 3
|
|
|
|
/* DSS has feature id */
|
|
enum dss_feat_id {
|
|
FEAT_GLOBAL_ALPHA = 1 << 0,
|
|
FEAT_GLOBAL_ALPHA_VID1 = 1 << 1,
|
|
FEAT_PRE_MULT_ALPHA = 1 << 2,
|
|
FEAT_LCDENABLEPOL = 1 << 3,
|
|
FEAT_LCDENABLESIGNAL = 1 << 4,
|
|
FEAT_PCKFREEENABLE = 1 << 5,
|
|
FEAT_FUNCGATED = 1 << 6,
|
|
FEAT_MGR_LCD2 = 1 << 7,
|
|
FEAT_LINEBUFFERSPLIT = 1 << 8,
|
|
FEAT_ROWREPEATENABLE = 1 << 9,
|
|
FEAT_RESIZECONF = 1 << 10,
|
|
/* Independent core clk divider */
|
|
FEAT_CORE_CLK_DIV = 1 << 11,
|
|
};
|
|
|
|
/* DSS register field id */
|
|
enum dss_feat_reg_field {
|
|
FEAT_REG_FIRHINC,
|
|
FEAT_REG_FIRVINC,
|
|
FEAT_REG_FIFOHIGHTHRESHOLD,
|
|
FEAT_REG_FIFOLOWTHRESHOLD,
|
|
FEAT_REG_FIFOSIZE,
|
|
FEAT_REG_HORIZONTALACCU,
|
|
FEAT_REG_VERTICALACCU,
|
|
};
|
|
|
|
/* DSS Feature Functions */
|
|
int dss_feat_get_num_mgrs(void);
|
|
int dss_feat_get_num_ovls(void);
|
|
unsigned long dss_feat_get_max_dss_fck(void);
|
|
enum omap_display_type dss_feat_get_supported_displays(enum omap_channel channel);
|
|
enum omap_color_mode dss_feat_get_supported_color_modes(enum omap_plane plane);
|
|
bool dss_feat_color_mode_supported(enum omap_plane plane,
|
|
enum omap_color_mode color_mode);
|
|
const char *dss_feat_get_clk_source_name(enum dss_clk_source id);
|
|
|
|
bool dss_has_feature(enum dss_feat_id id);
|
|
void dss_feat_get_reg_field(enum dss_feat_reg_field id, u8 *start, u8 *end);
|
|
void dss_features_init(void);
|
|
#endif
|