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859deea949
The Cell CPU timebase has an erratum. When reading the entire 64 bits of the timebase with one mftb instruction, there is a handful of cycles window during which one might read a value with the low order 32 bits already reset to 0x00000000 but the high order bits not yet incremeted by one. This fixes it by reading the timebase again until the low order 32 bits is no longer 0. That might introduce occasional latencies if hitting mftb just at the wrong time, but no more than 70ns on a cell blade, and that was considered acceptable. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Acked-by: Olof Johansson <olof@lixom.net> Signed-off-by: Paul Mackerras <paulus@samba.org>
49 lines
793 B
C
49 lines
793 B
C
#ifndef _ASM_POWERPC_TIMEX_H
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#define _ASM_POWERPC_TIMEX_H
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#ifdef __KERNEL__
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/*
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* PowerPC architecture timex specifications
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*/
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#include <asm/cputable.h>
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#include <asm/reg.h>
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#define CLOCK_TICK_RATE 1024000 /* Underlying HZ */
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typedef unsigned long cycles_t;
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static inline cycles_t get_cycles(void)
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{
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#ifdef __powerpc64__
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return mftb();
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#else
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cycles_t ret;
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/*
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* For the "cycle" counter we use the timebase lower half.
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* Currently only used on SMP.
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*/
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ret = 0;
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__asm__ __volatile__(
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"97: mftb %0\n"
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"99:\n"
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".section __ftr_fixup,\"a\"\n"
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".align 2\n"
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"98:\n"
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" .long %1\n"
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" .long 0\n"
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" .long 97b-98b\n"
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" .long 99b-98b\n"
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".previous"
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: "=r" (ret) : "i" (CPU_FTR_601));
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return ret;
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#endif
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}
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#endif /* __KERNEL__ */
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#endif /* _ASM_POWERPC_TIMEX_H */
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