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02ae2bc6fe
In common PLL designs, changes to the dividers take effect almost immediately, while changes to the multipliers (implemented as dividers in the feedback loop) take a few cycles to work into the feedback loop for the PLL to stablize. Sometimes when the PLL clock rate is changed, the decrease in the divider is too much for the decrease in the multiplier to catch up. The PLL clock rate will spike, and in some cases, might lock up completely. This is especially the case if the divider changed is the pre-divider, which affects the reference frequency. This patch introduces a clk notifier callback that will gate and then ungate a clk after a rate change, effectively resetting it, so it continues to work, despite any possible lockups. Care must be taken to reparent any consumers to other temporary clocks during the rate change, and that this notifier callback must be the first to be registered. This is intended to fix occasional lockups with cpufreq on newer Allwinner SoCs, such as the A33 and the H3. Previously it was thought that reparenting the cpu clock away from the PLL while it stabilized was enough, as this worked quite well on the A31. On the A33, hangs have been observed after cpufreq was recently introduced. With the H3, a more thorough test [1] showed that reparenting alone isn't enough. The system still locks up unless the dividers are limited to 1. A hunch was if the PLL was stuck in some unknown state, perhaps gating then ungating it would bring it back to normal. Tests done by Icenowy Zheng using Ondrej's test firmware shows this to be a valid solution. [1] http://www.spinics.net/lists/arm-kernel/msg552501.html Reported-by: Ondrej Jirman <megous@megous.com> Signed-off-by: Chen-Yu Tsai <wens@csie.org> Tested-by: Icenowy Zheng <icenowy@aosc.io> Tested-by: Quentin Schulz <quentin.schulz@free-electrons.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
102 lines
2.5 KiB
C
102 lines
2.5 KiB
C
/*
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* Copyright (c) 2016 Maxime Ripard. All rights reserved.
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*
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* This software is licensed under the terms of the GNU General Public
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* License version 2, as published by the Free Software Foundation, and
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* may be copied, distributed, and modified under those terms.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef _COMMON_H_
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#define _COMMON_H_
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#include <linux/compiler.h>
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#include <linux/clk-provider.h>
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#define CCU_FEATURE_FRACTIONAL BIT(0)
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#define CCU_FEATURE_VARIABLE_PREDIV BIT(1)
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#define CCU_FEATURE_FIXED_PREDIV BIT(2)
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#define CCU_FEATURE_FIXED_POSTDIV BIT(3)
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#define CCU_FEATURE_ALL_PREDIV BIT(4)
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#define CCU_FEATURE_LOCK_REG BIT(5)
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struct device_node;
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#define CLK_HW_INIT(_name, _parent, _ops, _flags) \
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&(struct clk_init_data) { \
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.flags = _flags, \
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.name = _name, \
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.parent_names = (const char *[]) { _parent }, \
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.num_parents = 1, \
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.ops = _ops, \
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}
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#define CLK_HW_INIT_PARENTS(_name, _parents, _ops, _flags) \
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&(struct clk_init_data) { \
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.flags = _flags, \
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.name = _name, \
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.parent_names = _parents, \
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.num_parents = ARRAY_SIZE(_parents), \
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.ops = _ops, \
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}
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#define CLK_FIXED_FACTOR(_struct, _name, _parent, \
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_div, _mult, _flags) \
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struct clk_fixed_factor _struct = { \
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.div = _div, \
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.mult = _mult, \
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.hw.init = CLK_HW_INIT(_name, \
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_parent, \
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&clk_fixed_factor_ops, \
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_flags), \
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}
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struct ccu_common {
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void __iomem *base;
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u16 reg;
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u16 lock_reg;
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u32 prediv;
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unsigned long features;
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spinlock_t *lock;
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struct clk_hw hw;
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};
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static inline struct ccu_common *hw_to_ccu_common(struct clk_hw *hw)
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{
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return container_of(hw, struct ccu_common, hw);
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}
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struct sunxi_ccu_desc {
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struct ccu_common **ccu_clks;
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unsigned long num_ccu_clks;
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struct clk_hw_onecell_data *hw_clks;
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struct ccu_reset_map *resets;
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unsigned long num_resets;
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};
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void ccu_helper_wait_for_lock(struct ccu_common *common, u32 lock);
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struct ccu_pll_nb {
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struct notifier_block clk_nb;
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struct ccu_common *common;
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u32 enable;
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u32 lock;
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};
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#define to_ccu_pll_nb(_nb) container_of(_nb, struct ccu_pll_nb, clk_nb)
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int ccu_pll_notifier_register(struct ccu_pll_nb *pll_nb);
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int sunxi_ccu_probe(struct device_node *node, void __iomem *reg,
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const struct sunxi_ccu_desc *desc);
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#endif /* _COMMON_H_ */
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