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https://github.com/edk2-porting/linux-next.git
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f38c02f3b3
Use irq_set_chip_and_handler() instead. Converted with coccinelle. Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
231 lines
5.6 KiB
C
231 lines
5.6 KiB
C
/*
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* Gemini gpiochip and interrupt routines
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*
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* Copyright (C) 2008-2009 Paulius Zaleckas <paulius.zaleckas@teltonika.lt>
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*
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* Based on plat-mxc/gpio.c:
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* MXC GPIO support. (c) 2008 Daniel Mack <daniel@caiaq.de>
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* Copyright 2008 Juergen Beisert, kernel@pengutronix.de
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*/
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/io.h>
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#include <linux/irq.h>
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#include <linux/gpio.h>
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#include <mach/hardware.h>
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#include <mach/irqs.h>
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#define GPIO_BASE(x) IO_ADDRESS(GEMINI_GPIO_BASE(x))
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/* GPIO registers definition */
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#define GPIO_DATA_OUT 0x0
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#define GPIO_DATA_IN 0x4
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#define GPIO_DIR 0x8
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#define GPIO_DATA_SET 0x10
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#define GPIO_DATA_CLR 0x14
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#define GPIO_PULL_EN 0x18
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#define GPIO_PULL_TYPE 0x1C
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#define GPIO_INT_EN 0x20
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#define GPIO_INT_STAT 0x24
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#define GPIO_INT_MASK 0x2C
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#define GPIO_INT_CLR 0x30
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#define GPIO_INT_TYPE 0x34
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#define GPIO_INT_BOTH_EDGE 0x38
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#define GPIO_INT_LEVEL 0x3C
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#define GPIO_DEBOUNCE_EN 0x40
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#define GPIO_DEBOUNCE_PRESCALE 0x44
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#define GPIO_PORT_NUM 3
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static void _set_gpio_irqenable(unsigned int base, unsigned int index,
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int enable)
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{
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unsigned int reg;
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reg = __raw_readl(base + GPIO_INT_EN);
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reg = (reg & (~(1 << index))) | (!!enable << index);
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__raw_writel(reg, base + GPIO_INT_EN);
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}
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static void gpio_ack_irq(struct irq_data *d)
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{
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unsigned int gpio = irq_to_gpio(d->irq);
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unsigned int base = GPIO_BASE(gpio / 32);
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__raw_writel(1 << (gpio % 32), base + GPIO_INT_CLR);
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}
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static void gpio_mask_irq(struct irq_data *d)
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{
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unsigned int gpio = irq_to_gpio(d->irq);
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unsigned int base = GPIO_BASE(gpio / 32);
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_set_gpio_irqenable(base, gpio % 32, 0);
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}
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static void gpio_unmask_irq(struct irq_data *d)
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{
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unsigned int gpio = irq_to_gpio(d->irq);
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unsigned int base = GPIO_BASE(gpio / 32);
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_set_gpio_irqenable(base, gpio % 32, 1);
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}
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static int gpio_set_irq_type(struct irq_data *d, unsigned int type)
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{
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unsigned int gpio = irq_to_gpio(d->irq);
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unsigned int gpio_mask = 1 << (gpio % 32);
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unsigned int base = GPIO_BASE(gpio / 32);
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unsigned int reg_both, reg_level, reg_type;
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reg_type = __raw_readl(base + GPIO_INT_TYPE);
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reg_level = __raw_readl(base + GPIO_INT_LEVEL);
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reg_both = __raw_readl(base + GPIO_INT_BOTH_EDGE);
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switch (type) {
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case IRQ_TYPE_EDGE_BOTH:
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reg_type &= ~gpio_mask;
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reg_both |= gpio_mask;
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break;
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case IRQ_TYPE_EDGE_RISING:
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reg_type &= ~gpio_mask;
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reg_both &= ~gpio_mask;
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reg_level &= ~gpio_mask;
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break;
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case IRQ_TYPE_EDGE_FALLING:
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reg_type &= ~gpio_mask;
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reg_both &= ~gpio_mask;
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reg_level |= gpio_mask;
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break;
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case IRQ_TYPE_LEVEL_HIGH:
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reg_type |= gpio_mask;
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reg_level &= ~gpio_mask;
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break;
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case IRQ_TYPE_LEVEL_LOW:
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reg_type |= gpio_mask;
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reg_level |= gpio_mask;
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break;
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default:
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return -EINVAL;
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}
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__raw_writel(reg_type, base + GPIO_INT_TYPE);
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__raw_writel(reg_level, base + GPIO_INT_LEVEL);
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__raw_writel(reg_both, base + GPIO_INT_BOTH_EDGE);
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gpio_ack_irq(d->irq);
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return 0;
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}
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static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
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{
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unsigned int port = (unsigned int)irq_desc_get_handler_data(desc);
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unsigned int gpio_irq_no, irq_stat;
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irq_stat = __raw_readl(GPIO_BASE(port) + GPIO_INT_STAT);
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gpio_irq_no = GPIO_IRQ_BASE + port * 32;
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for (; irq_stat != 0; irq_stat >>= 1, gpio_irq_no++) {
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if ((irq_stat & 1) == 0)
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continue;
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generic_handle_irq(gpio_irq_no);
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}
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}
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static struct irq_chip gpio_irq_chip = {
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.name = "GPIO",
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.irq_ack = gpio_ack_irq,
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.irq_mask = gpio_mask_irq,
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.irq_unmask = gpio_unmask_irq,
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.irq_set_type = gpio_set_irq_type,
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};
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static void _set_gpio_direction(struct gpio_chip *chip, unsigned offset,
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int dir)
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{
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unsigned int base = GPIO_BASE(offset / 32);
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unsigned int reg;
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reg = __raw_readl(base + GPIO_DIR);
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if (dir)
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reg |= 1 << (offset % 32);
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else
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reg &= ~(1 << (offset % 32));
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__raw_writel(reg, base + GPIO_DIR);
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}
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static void gemini_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
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{
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unsigned int base = GPIO_BASE(offset / 32);
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if (value)
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__raw_writel(1 << (offset % 32), base + GPIO_DATA_SET);
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else
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__raw_writel(1 << (offset % 32), base + GPIO_DATA_CLR);
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}
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static int gemini_gpio_get(struct gpio_chip *chip, unsigned offset)
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{
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unsigned int base = GPIO_BASE(offset / 32);
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return (__raw_readl(base + GPIO_DATA_IN) >> (offset % 32)) & 1;
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}
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static int gemini_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
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{
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_set_gpio_direction(chip, offset, 0);
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return 0;
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}
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static int gemini_gpio_direction_output(struct gpio_chip *chip, unsigned offset,
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int value)
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{
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_set_gpio_direction(chip, offset, 1);
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gemini_gpio_set(chip, offset, value);
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return 0;
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}
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static struct gpio_chip gemini_gpio_chip = {
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.label = "Gemini",
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.direction_input = gemini_gpio_direction_input,
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.get = gemini_gpio_get,
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.direction_output = gemini_gpio_direction_output,
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.set = gemini_gpio_set,
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.base = 0,
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.ngpio = GPIO_PORT_NUM * 32,
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};
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void __init gemini_gpio_init(void)
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{
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int i, j;
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for (i = 0; i < GPIO_PORT_NUM; i++) {
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/* disable, unmask and clear all interrupts */
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__raw_writel(0x0, GPIO_BASE(i) + GPIO_INT_EN);
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__raw_writel(0x0, GPIO_BASE(i) + GPIO_INT_MASK);
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__raw_writel(~0x0, GPIO_BASE(i) + GPIO_INT_CLR);
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for (j = GPIO_IRQ_BASE + i * 32;
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j < GPIO_IRQ_BASE + (i + 1) * 32; j++) {
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irq_set_chip_and_handler(j, &gpio_irq_chip,
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handle_edge_irq);
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set_irq_flags(j, IRQF_VALID);
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}
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irq_set_chained_handler(IRQ_GPIO(i), gpio_irq_handler);
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irq_set_handler_data(IRQ_GPIO(i), (void *)i);
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}
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BUG_ON(gpiochip_add(&gemini_gpio_chip));
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}
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