Markos Chandras 5aed9da128 MIPS: Add LLB bit and related feature for the Config 5 CP0 register ... The LLBIT (bit 4) in the Config5 CP0 register indicates the software availability of the Load-Linked bit. This bit is only set by hardware and it has the following meaning: 0: LLB functionality is not supported 1: LLB functionality is supported. The following feature are also supported: - ERETNC instruction. Similar to ERET but it does not clear the LLB bit in the LLAddr register. - CP0 LLAddr/LLB bit must be set - LLbit is software accessible through the LLAddr[0] This will be used later on to emulate R2 LL/SC instructions. Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>		2015-02-17 15:37:36 +00:00
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asm	MIPS: Add LLB bit and related feature for the Config 5 CP0 register	2015-02-17 15:37:36 +00:00
uapi/asm	MIPS: Emulate the new MIPS R6 BNEZC and JIALC instructions	2015-02-17 15:37:35 +00:00