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4cbe1bfa27
The 800x600 (SVGA) screen resolution was lacking in the set of built-in selectable EDID screen resolutions that can be used to repair misbehaving monitor firmware. This patch adds the related data set and expands the documentation. Note that the SVGA bit occupies a different byte to all the existing users of the established timing bits forcing a rework of the ESTABLISHED_TIMINGS_BITS macro. Tested new EDID on an aged (and misbehaving) industrial LCD panel; existing EDIDs still pass edid-decode's checksum checks. Signed-off-by: Daniel Thompson <daniel.thompson@linaro.org> Cc: Randy Dunlap <rdunlap@infradead.org> Cc: David Airlie <airlied@linux.ie> Cc: Carsten Emde <C.Emde@osadl.org> Cc: linux-doc@vger.kernel.org Cc: dri-devel@lists.freedesktop.org Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
273 lines
9.5 KiB
ArmAsm
273 lines
9.5 KiB
ArmAsm
/*
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edid.S: EDID data template
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Copyright (C) 2012 Carsten Emde <C.Emde@osadl.org>
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This program is free software; you can redistribute it and/or
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modify it under the terms of the GNU General Public License
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as published by the Free Software Foundation; either version 2
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of the License, or (at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
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*/
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/* Manufacturer */
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#define MFG_LNX1 'L'
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#define MFG_LNX2 'N'
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#define MFG_LNX3 'X'
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#define SERIAL 0
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#define YEAR 2012
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#define WEEK 5
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/* EDID 1.3 standard definitions */
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#define XY_RATIO_16_10 0b00
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#define XY_RATIO_4_3 0b01
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#define XY_RATIO_5_4 0b10
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#define XY_RATIO_16_9 0b11
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/* Provide defaults for the timing bits */
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#ifndef ESTABLISHED_TIMING1_BITS
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#define ESTABLISHED_TIMING1_BITS 0x00
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#endif
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#ifndef ESTABLISHED_TIMING2_BITS
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#define ESTABLISHED_TIMING2_BITS 0x00
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#endif
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#ifndef ESTABLISHED_TIMING3_BITS
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#define ESTABLISHED_TIMING3_BITS 0x00
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#endif
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#define mfgname2id(v1,v2,v3) \
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((((v1-'@')&0x1f)<<10)+(((v2-'@')&0x1f)<<5)+((v3-'@')&0x1f))
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#define swap16(v1) ((v1>>8)+((v1&0xff)<<8))
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#define msbs2(v1,v2) ((((v1>>8)&0x0f)<<4)+((v2>>8)&0x0f))
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#define msbs4(v1,v2,v3,v4) \
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(((v1&0x03)>>2)+((v2&0x03)>>4)+((v3&0x03)>>6)+((v4&0x03)>>8))
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#define pixdpi2mm(pix,dpi) ((pix*25)/dpi)
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#define xsize pixdpi2mm(XPIX,DPI)
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#define ysize pixdpi2mm(YPIX,DPI)
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.data
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/* Fixed header pattern */
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header: .byte 0x00,0xff,0xff,0xff,0xff,0xff,0xff,0x00
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mfg_id: .word swap16(mfgname2id(MFG_LNX1, MFG_LNX2, MFG_LNX3))
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prod_code: .word 0
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/* Serial number. 32 bits, little endian. */
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serial_number: .long SERIAL
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/* Week of manufacture */
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week: .byte WEEK
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/* Year of manufacture, less 1990. (1990-2245)
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If week=255, it is the model year instead */
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year: .byte YEAR-1990
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version: .byte VERSION /* EDID version, usually 1 (for 1.3) */
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revision: .byte REVISION /* EDID revision, usually 3 (for 1.3) */
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/* If Bit 7=1 Digital input. If set, the following bit definitions apply:
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Bits 6-1 Reserved, must be 0
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Bit 0 Signal is compatible with VESA DFP 1.x TMDS CRGB,
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1 pixel per clock, up to 8 bits per color, MSB aligned,
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If Bit 7=0 Analog input. If clear, the following bit definitions apply:
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Bits 6-5 Video white and sync levels, relative to blank
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00=+0.7/-0.3 V; 01=+0.714/-0.286 V;
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10=+1.0/-0.4 V; 11=+0.7/0 V
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Bit 4 Blank-to-black setup (pedestal) expected
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Bit 3 Separate sync supported
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Bit 2 Composite sync (on HSync) supported
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Bit 1 Sync on green supported
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Bit 0 VSync pulse must be serrated when somposite or
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sync-on-green is used. */
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video_parms: .byte 0x6d
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/* Maximum horizontal image size, in centimetres
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(max 292 cm/115 in at 16:9 aspect ratio) */
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max_hor_size: .byte xsize/10
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/* Maximum vertical image size, in centimetres.
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If either byte is 0, undefined (e.g. projector) */
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max_vert_size: .byte ysize/10
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/* Display gamma, minus 1, times 100 (range 1.00-3.5 */
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gamma: .byte 120
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/* Bit 7 DPMS standby supported
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Bit 6 DPMS suspend supported
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Bit 5 DPMS active-off supported
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Bits 4-3 Display type: 00=monochrome; 01=RGB colour;
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10=non-RGB multicolour; 11=undefined
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Bit 2 Standard sRGB colour space. Bytes 25-34 must contain
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sRGB standard values.
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Bit 1 Preferred timing mode specified in descriptor block 1.
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Bit 0 GTF supported with default parameter values. */
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dsp_features: .byte 0xea
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/* Chromaticity coordinates. */
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/* Red and green least-significant bits
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Bits 7-6 Red x value least-significant 2 bits
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Bits 5-4 Red y value least-significant 2 bits
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Bits 3-2 Green x value lst-significant 2 bits
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Bits 1-0 Green y value least-significant 2 bits */
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red_green_lsb: .byte 0x5e
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/* Blue and white least-significant 2 bits */
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blue_white_lsb: .byte 0xc0
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/* Red x value most significant 8 bits.
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0-255 encodes 0-0.996 (255/256); 0-0.999 (1023/1024) with lsbits */
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red_x_msb: .byte 0xa4
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/* Red y value most significant 8 bits */
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red_y_msb: .byte 0x59
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/* Green x and y value most significant 8 bits */
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green_x_y_msb: .byte 0x4a,0x98
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/* Blue x and y value most significant 8 bits */
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blue_x_y_msb: .byte 0x25,0x20
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/* Default white point x and y value most significant 8 bits */
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white_x_y_msb: .byte 0x50,0x54
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/* Established timings */
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/* Bit 7 720x400 @ 70 Hz
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Bit 6 720x400 @ 88 Hz
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Bit 5 640x480 @ 60 Hz
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Bit 4 640x480 @ 67 Hz
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Bit 3 640x480 @ 72 Hz
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Bit 2 640x480 @ 75 Hz
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Bit 1 800x600 @ 56 Hz
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Bit 0 800x600 @ 60 Hz */
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estbl_timing1: .byte ESTABLISHED_TIMING1_BITS
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/* Bit 7 800x600 @ 72 Hz
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Bit 6 800x600 @ 75 Hz
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Bit 5 832x624 @ 75 Hz
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Bit 4 1024x768 @ 87 Hz, interlaced (1024x768)
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Bit 3 1024x768 @ 60 Hz
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Bit 2 1024x768 @ 72 Hz
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Bit 1 1024x768 @ 75 Hz
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Bit 0 1280x1024 @ 75 Hz */
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estbl_timing2: .byte ESTABLISHED_TIMING2_BITS
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/* Bit 7 1152x870 @ 75 Hz (Apple Macintosh II)
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Bits 6-0 Other manufacturer-specific display mod */
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estbl_timing3: .byte ESTABLISHED_TIMING3_BITS
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/* Standard timing */
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/* X resolution, less 31, divided by 8 (256-2288 pixels) */
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std_xres: .byte (XPIX/8)-31
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/* Y resolution, X:Y pixel ratio
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Bits 7-6 X:Y pixel ratio: 00=16:10; 01=4:3; 10=5:4; 11=16:9.
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Bits 5-0 Vertical frequency, less 60 (60-123 Hz) */
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std_vres: .byte (XY_RATIO<<6)+VFREQ-60
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.fill 7,2,0x0101 /* Unused */
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descriptor1:
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/* Pixel clock in 10 kHz units. (0.-655.35 MHz, little-endian) */
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clock: .word CLOCK/10
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/* Horizontal active pixels 8 lsbits (0-4095) */
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x_act_lsb: .byte XPIX&0xff
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/* Horizontal blanking pixels 8 lsbits (0-4095)
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End of active to start of next active. */
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x_blk_lsb: .byte XBLANK&0xff
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/* Bits 7-4 Horizontal active pixels 4 msbits
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Bits 3-0 Horizontal blanking pixels 4 msbits */
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x_msbs: .byte msbs2(XPIX,XBLANK)
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/* Vertical active lines 8 lsbits (0-4095) */
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y_act_lsb: .byte YPIX&0xff
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/* Vertical blanking lines 8 lsbits (0-4095) */
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y_blk_lsb: .byte YBLANK&0xff
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/* Bits 7-4 Vertical active lines 4 msbits
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Bits 3-0 Vertical blanking lines 4 msbits */
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y_msbs: .byte msbs2(YPIX,YBLANK)
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/* Horizontal sync offset pixels 8 lsbits (0-1023) From blanking start */
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x_snc_off_lsb: .byte XOFFSET&0xff
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/* Horizontal sync pulse width pixels 8 lsbits (0-1023) */
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x_snc_pls_lsb: .byte XPULSE&0xff
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/* Bits 7-4 Vertical sync offset lines 4 lsbits -63)
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Bits 3-0 Vertical sync pulse width lines 4 lsbits -63) */
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y_snc_lsb: .byte ((YOFFSET-63)<<4)+(YPULSE-63)
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/* Bits 7-6 Horizontal sync offset pixels 2 msbits
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Bits 5-4 Horizontal sync pulse width pixels 2 msbits
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Bits 3-2 Vertical sync offset lines 2 msbits
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Bits 1-0 Vertical sync pulse width lines 2 msbits */
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xy_snc_msbs: .byte msbs4(XOFFSET,XPULSE,YOFFSET,YPULSE)
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/* Horizontal display size, mm, 8 lsbits (0-4095 mm, 161 in) */
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x_dsp_size: .byte xsize&0xff
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/* Vertical display size, mm, 8 lsbits (0-4095 mm, 161 in) */
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y_dsp_size: .byte ysize&0xff
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/* Bits 7-4 Horizontal display size, mm, 4 msbits
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Bits 3-0 Vertical display size, mm, 4 msbits */
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dsp_size_mbsb: .byte msbs2(xsize,ysize)
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/* Horizontal border pixels (each side; total is twice this) */
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x_border: .byte 0
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/* Vertical border lines (each side; total is twice this) */
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y_border: .byte 0
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/* Bit 7 Interlaced
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Bits 6-5 Stereo mode: 00=No stereo; other values depend on bit 0:
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Bit 0=0: 01=Field sequential, sync=1 during right; 10=similar,
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sync=1 during left; 11=4-way interleaved stereo
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Bit 0=1 2-way interleaved stereo: 01=Right image on even lines;
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10=Left image on even lines; 11=side-by-side
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Bits 4-3 Sync type: 00=Analog composite; 01=Bipolar analog composite;
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10=Digital composite (on HSync); 11=Digital separate
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Bit 2 If digital separate: Vertical sync polarity (1=positive)
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Other types: VSync serrated (HSync during VSync)
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Bit 1 If analog sync: Sync on all 3 RGB lines (else green only)
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Digital: HSync polarity (1=positive)
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Bit 0 2-way line-interleaved stereo, if bits 4-3 are not 00. */
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features: .byte 0x18+(VSYNC_POL<<2)+(HSYNC_POL<<1)
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descriptor2: .byte 0,0 /* Not a detailed timing descriptor */
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.byte 0 /* Must be zero */
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.byte 0xff /* Descriptor is monitor serial number (text) */
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.byte 0 /* Must be zero */
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start1: .ascii "Linux #0"
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end1: .byte 0x0a /* End marker */
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.fill 12-(end1-start1), 1, 0x20 /* Padded spaces */
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descriptor3: .byte 0,0 /* Not a detailed timing descriptor */
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.byte 0 /* Must be zero */
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.byte 0xfd /* Descriptor is monitor range limits */
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.byte 0 /* Must be zero */
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start2: .byte VFREQ-1 /* Minimum vertical field rate (1-255 Hz) */
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.byte VFREQ+1 /* Maximum vertical field rate (1-255 Hz) */
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.byte (CLOCK/(XPIX+XBLANK))-1 /* Minimum horizontal line rate
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(1-255 kHz) */
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.byte (CLOCK/(XPIX+XBLANK))+1 /* Maximum horizontal line rate
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(1-255 kHz) */
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.byte (CLOCK/10000)+1 /* Maximum pixel clock rate, rounded up
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to 10 MHz multiple (10-2550 MHz) */
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.byte 0 /* No extended timing information type */
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end2: .byte 0x0a /* End marker */
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.fill 12-(end2-start2), 1, 0x20 /* Padded spaces */
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descriptor4: .byte 0,0 /* Not a detailed timing descriptor */
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.byte 0 /* Must be zero */
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.byte 0xfc /* Descriptor is text */
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.byte 0 /* Must be zero */
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start3: .ascii TIMING_NAME
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end3: .byte 0x0a /* End marker */
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.fill 12-(end3-start3), 1, 0x20 /* Padded spaces */
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extensions: .byte 0 /* Number of extensions to follow */
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checksum: .byte CRC /* Sum of all bytes must be 0 */
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