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8263a67e16
This adds support for extended ASIDs (up to 16-bits) on newer SH-X3 cores that implement the PTAEX register and respective functionality. Presently only the 65nm SH7786 (90nm only supports legacy 8-bit ASIDs). The main change is in how the PTE is written out when loading the entry in to the TLB, as well as in how the TLB entry is selectively flushed. While SH-X2 extended mode splits out the memory-mapped U and I-TLB data arrays for extra bits, extended ASID mode splits out the address arrays. While we don't use the memory-mapped data array access, the address array accesses are necessary for selective TLB flushes, so these are implemented newly and replace the generic SH-4 implementation. With this, TLB flushes in switch_mm() are almost non-existent on newer parts. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
27 lines
1.0 KiB
C
27 lines
1.0 KiB
C
#ifndef __ASM_SH_CPU_FEATURES_H
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#define __ASM_SH_CPU_FEATURES_H
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/*
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* Processor flags
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*
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* Note: When adding a new flag, keep cpu_flags[] in
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* arch/sh/kernel/setup.c in sync so symbolic name
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* mapping of the processor flags has a chance of being
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* reasonably accurate.
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*
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* These flags are also available through the ELF
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* auxiliary vector as AT_HWCAP.
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*/
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#define CPU_HAS_FPU 0x0001 /* Hardware FPU support */
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#define CPU_HAS_P2_FLUSH_BUG 0x0002 /* Need to flush the cache in P2 area */
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#define CPU_HAS_MMU_PAGE_ASSOC 0x0004 /* SH3: TLB way selection bit support */
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#define CPU_HAS_DSP 0x0008 /* SH-DSP: DSP support */
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#define CPU_HAS_PERF_COUNTER 0x0010 /* Hardware performance counters */
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#define CPU_HAS_PTEA 0x0020 /* PTEA register */
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#define CPU_HAS_LLSC 0x0040 /* movli.l/movco.l */
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#define CPU_HAS_L2_CACHE 0x0080 /* Secondary cache / URAM */
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#define CPU_HAS_OP32 0x0100 /* 32-bit instruction support */
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#define CPU_HAS_PTEAEX 0x0200 /* PTE ASID Extension support */
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#endif /* __ASM_SH_CPU_FEATURES_H */
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