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https://github.com/edk2-porting/linux-next.git
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acbde1db29
The existing code relied on the hardware definition (<arch/chip.h>) to specify how much VA and PA space was available. It's convenient to allow customizing this for some configurations, so provide symbols MAX_PA_WIDTH and MAX_VA_WIDTH in <asm/page.h> that can be modified if desired. Additionally, move away from the MEM_XX_INTRPT nomenclature to define the start of various regions within the VA space. In fact the cleaner symbol is, for example, MEM_SV_START, to indicate the start of the area used for supervisor code; the actual address of the interrupt vectors is not as important, and can be changed if desired. As part of this change, convert from "intrpt1" nomenclature (which built in the old privilege-level 1 model) to a simple "intrpt". Also strip out some tilepro-specific code supporting modifying the PL the kernel could run at, since we don't actually support using different PLs in tilepro, only tilegx. Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>
184 lines
4.8 KiB
ArmAsm
184 lines
4.8 KiB
ArmAsm
/*
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* Copyright 2010 Tilera Corporation. All Rights Reserved.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation, version 2.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
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* NON INFRINGEMENT. See the GNU General Public License for
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* more details.
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*
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* TILE startup code.
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*/
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#include <linux/linkage.h>
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#include <linux/init.h>
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#include <asm/page.h>
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#include <asm/pgtable.h>
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#include <asm/thread_info.h>
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#include <asm/processor.h>
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#include <asm/asm-offsets.h>
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#include <hv/hypervisor.h>
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#include <arch/chip.h>
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#include <arch/spr_def.h>
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/*
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* This module contains the entry code for kernel images. It performs the
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* minimal setup needed to call the generic C routines.
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*/
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__HEAD
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ENTRY(_start)
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/* Notify the hypervisor of what version of the API we want */
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{
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movei r1, TILE_CHIP
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movei r2, TILE_CHIP_REV
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}
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{
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moveli r0, _HV_VERSION_OLD_HV_INIT
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jal _hv_init
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}
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/* Get a reasonable default ASID in r0 */
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{
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move r0, zero
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jal _hv_inquire_asid
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}
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/* Install the default page table */
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{
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moveli r6, lo16(swapper_pgprot - PAGE_OFFSET)
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move r4, r0 /* use starting ASID of range for this page table */
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}
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{
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moveli r0, lo16(swapper_pg_dir - PAGE_OFFSET)
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auli r6, r6, ha16(swapper_pgprot - PAGE_OFFSET)
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}
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{
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lw r2, r6
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addi r6, r6, 4
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}
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{
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lw r3, r6
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auli r0, r0, ha16(swapper_pg_dir - PAGE_OFFSET)
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}
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{
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finv r6
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move r1, zero /* high 32 bits of CPA is zero */
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}
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{
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moveli lr, lo16(1f)
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moveli r5, CTX_PAGE_FLAG
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}
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{
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auli lr, lr, ha16(1f)
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j _hv_install_context
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}
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1:
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/* Get our processor number and save it away in SAVE_K_0. */
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jal _hv_inquire_topology
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mulll_uu r4, r1, r2 /* r1 == y, r2 == width */
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add r4, r4, r0 /* r0 == x, so r4 == cpu == y*width + x */
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#ifdef CONFIG_SMP
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/*
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* Load up our per-cpu offset. When the first (master) tile
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* boots, this value is still zero, so we will load boot_pc
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* with start_kernel, and boot_sp at the top of init_stack.
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* The master tile initializes the per-cpu offset array, so that
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* when subsequent (secondary) tiles boot, they will instead load
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* from their per-cpu versions of boot_sp and boot_pc.
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*/
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moveli r5, lo16(__per_cpu_offset)
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auli r5, r5, ha16(__per_cpu_offset)
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s2a r5, r4, r5
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lw r5, r5
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bnz r5, 1f
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/*
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* Save the width and height to the smp_topology variable
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* for later use.
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*/
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moveli r0, lo16(smp_topology + HV_TOPOLOGY_WIDTH_OFFSET)
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auli r0, r0, ha16(smp_topology + HV_TOPOLOGY_WIDTH_OFFSET)
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{
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sw r0, r2
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addi r0, r0, (HV_TOPOLOGY_HEIGHT_OFFSET - HV_TOPOLOGY_WIDTH_OFFSET)
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}
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sw r0, r3
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1:
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#else
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move r5, zero
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#endif
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/* Load and go with the correct pc and sp. */
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{
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addli r1, r5, lo16(boot_sp)
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addli r0, r5, lo16(boot_pc)
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}
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{
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auli r1, r1, ha16(boot_sp)
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auli r0, r0, ha16(boot_pc)
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}
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lw r0, r0
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lw sp, r1
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or r4, sp, r4
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mtspr SPR_SYSTEM_SAVE_K_0, r4 /* save ksp0 + cpu */
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{
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move lr, zero /* stop backtraces in the called function */
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jr r0
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}
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ENDPROC(_start)
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__PAGE_ALIGNED_BSS
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.align PAGE_SIZE
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ENTRY(empty_zero_page)
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.fill PAGE_SIZE,1,0
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END(empty_zero_page)
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.macro PTE va, cpa, bits1, no_org=0
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.ifeq \no_org
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.org swapper_pg_dir + PGD_INDEX(\va) * HV_PTE_SIZE
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.endif
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.word HV_PTE_PAGE | HV_PTE_DIRTY | HV_PTE_PRESENT | HV_PTE_ACCESSED | \
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(HV_PTE_MODE_CACHE_NO_L3 << HV_PTE_INDEX_MODE)
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.word (\bits1) | (HV_CPA_TO_PTFN(\cpa) << (HV_PTE_INDEX_PTFN - 32))
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.endm
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__PAGE_ALIGNED_DATA
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.align PAGE_SIZE
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ENTRY(swapper_pg_dir)
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/*
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* All data pages from PAGE_OFFSET to MEM_USER_INTRPT are mapped as
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* VA = PA + PAGE_OFFSET. We remap things with more precise access
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* permissions and more respect for size of RAM later.
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*/
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.set addr, 0
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.rept (MEM_USER_INTRPT - PAGE_OFFSET) >> PGDIR_SHIFT
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PTE addr + PAGE_OFFSET, addr, (1 << (HV_PTE_INDEX_READABLE - 32)) | \
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(1 << (HV_PTE_INDEX_WRITABLE - 32))
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.set addr, addr + PGDIR_SIZE
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.endr
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/* The true text VAs are mapped as VA = PA + MEM_SV_START */
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PTE MEM_SV_START, 0, (1 << (HV_PTE_INDEX_READABLE - 32)) | \
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(1 << (HV_PTE_INDEX_EXECUTABLE - 32))
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.org swapper_pg_dir + PGDIR_SIZE
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END(swapper_pg_dir)
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/*
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* Isolate swapper_pgprot to its own cache line, since each cpu
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* starting up will read it using VA-is-PA and local homing.
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* This would otherwise likely conflict with other data on the cache
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* line, once we have set its permanent home in the page tables.
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*/
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__INITDATA
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.align CHIP_L2_LINE_SIZE()
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ENTRY(swapper_pgprot)
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PTE 0, 0, (1 << (HV_PTE_INDEX_READABLE - 32)) | \
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(1 << (HV_PTE_INDEX_WRITABLE - 32)), 1
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.align CHIP_L2_LINE_SIZE()
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END(swapper_pgprot)
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