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5a31be3fb5
Here is a small patch to automatically detect the DRAM size on m520x. It was generated against 2.6.17-uc0, and tested on an Intec 5208 dev board. (This part of the patch if the memory register defines for the 520x ColdFire CPU family - Greg). Signed-off-by: Michael Broughton <mbobowik@telusplanet.net> Signed-off-by: Greg Ungerer <gerg@uclinux.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
64 lines
2.6 KiB
C
64 lines
2.6 KiB
C
/****************************************************************************/
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/*
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* m520xsim.h -- ColdFire 5207/5208 System Integration Module support.
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*
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* (C) Copyright 2005, Intec Automation (mike@steroidmicros.com)
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*/
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/****************************************************************************/
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#ifndef m520xsim_h
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#define m520xsim_h
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/****************************************************************************/
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/*
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* Define the 5282 SIM register set addresses.
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*/
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#define MCFICM_INTC0 0x48000 /* Base for Interrupt Ctrl 0 */
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#define MCFINTC_IPRH 0x00 /* Interrupt pending 32-63 */
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#define MCFINTC_IPRL 0x04 /* Interrupt pending 1-31 */
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#define MCFINTC_IMRH 0x08 /* Interrupt mask 32-63 */
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#define MCFINTC_IMRL 0x0c /* Interrupt mask 1-31 */
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#define MCFINTC_INTFRCH 0x10 /* Interrupt force 32-63 */
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#define MCFINTC_INTFRCL 0x14 /* Interrupt force 1-31 */
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#define MCFINTC_ICR0 0x40 /* Base ICR register */
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#define MCFINT_VECBASE 64
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#define MCFINT_UART0 26 /* Interrupt number for UART0 */
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#define MCFINT_UART1 27 /* Interrupt number for UART1 */
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#define MCFINT_UART2 28 /* Interrupt number for UART2 */
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#define MCFINT_QSPI 31 /* Interrupt number for QSPI */
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#define MCFINT_PIT1 4 /* Interrupt number for PIT1 (PIT0 in processor) */
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/*
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* SDRAM configuration registers.
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*/
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#define MCFSIM_SDMR 0x000a8000 /* SDRAM Mode/Extended Mode Register */
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#define MCFSIM_SDCR 0x000a8004 /* SDRAM Control Register */
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#define MCFSIM_SDCFG1 0x000a8008 /* SDRAM Configuration Register 1 */
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#define MCFSIM_SDCFG2 0x000a800c /* SDRAM Configuration Register 2 */
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#define MCFSIM_SDCS0 0x000a8110 /* SDRAM Chip Select 0 Configuration */
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#define MCFSIM_SDCS1 0x000a8114 /* SDRAM Chip Select 1 Configuration */
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#define MCF_GPIO_PAR_UART (0xA4036)
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#define MCF_GPIO_PAR_FECI2C (0xA4033)
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#define MCF_GPIO_PAR_FEC (0xA4038)
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#define MCF_GPIO_PAR_UART_PAR_URXD0 (0x0001)
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#define MCF_GPIO_PAR_UART_PAR_UTXD0 (0x0002)
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#define MCF_GPIO_PAR_UART_PAR_URXD1 (0x0040)
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#define MCF_GPIO_PAR_UART_PAR_UTXD1 (0x0080)
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#define MCF_GPIO_PAR_FECI2C_PAR_SDA_URXD2 (0x02)
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#define MCF_GPIO_PAR_FECI2C_PAR_SCL_UTXD2 (0x04)
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#define ICR_INTRCONF 0x05
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#define MCFPIT_IMR MCFINTC_IMRL
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#define MCFPIT_IMR_IBIT (1 << MCFINT_PIT1)
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/****************************************************************************/
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#endif /* m520xsim_h */
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