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This adds the binding documentation for the Imagination Technologies hash accelerator that provides hardware acceleration for SHA1/SHA224/SHA256/MD5 hashes. This hardware will be present in the upcoming pistachio SoC. Signed-off-by: James Hartley <james.hartley@imgtec.com> Reviewed-by: Andrew Bresticker <abrestic@chromium.org> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au> |
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amd-ccp.txt | ||
atmel-crypto.txt | ||
fsl-dcp.txt | ||
fsl-imx-sahara.txt | ||
fsl-sec2.txt | ||
fsl-sec4.txt | ||
fsl-sec6.txt | ||
img-hash.txt | ||
mv_cesa.txt | ||
omap-aes.txt | ||
omap-des.txt | ||
omap-sham.txt | ||
picochip-spacc.txt | ||
qcom-qce.txt | ||
samsung-sss.txt |