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c5102f5935
The cacheflush syscall can fail for two reasons: (1) The arguments are invalid (nonsensical address range or no VMA) (2) The region generates a translation fault on a VIPT or PIPT cache This patch allows do_cache_op to return an error code to userspace in the case of the above. The various coherent_user_range implementations are modified to return 0 in the case of VIVT caches or -EFAULT in the case of an abort on v6/v7 cores. Reviewed-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
147 lines
3.1 KiB
ArmAsm
147 lines
3.1 KiB
ArmAsm
/*
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* linux/arch/arm/mm/cache-v4.S
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*
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* Copyright (C) 1997-2002 Russell king
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/linkage.h>
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#include <linux/init.h>
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#include <asm/page.h>
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#include "proc-macros.S"
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/*
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* flush_icache_all()
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*
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* Unconditionally clean and invalidate the entire icache.
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*/
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ENTRY(v4_flush_icache_all)
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mov pc, lr
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ENDPROC(v4_flush_icache_all)
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/*
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* flush_user_cache_all()
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*
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* Invalidate all cache entries in a particular address
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* space.
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*
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* - mm - mm_struct describing address space
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*/
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ENTRY(v4_flush_user_cache_all)
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/* FALLTHROUGH */
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/*
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* flush_kern_cache_all()
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*
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* Clean and invalidate the entire cache.
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*/
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ENTRY(v4_flush_kern_cache_all)
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#ifdef CONFIG_CPU_CP15
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mov r0, #0
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mcr p15, 0, r0, c7, c7, 0 @ flush ID cache
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mov pc, lr
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#else
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/* FALLTHROUGH */
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#endif
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/*
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* flush_user_cache_range(start, end, flags)
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*
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* Invalidate a range of cache entries in the specified
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* address space.
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*
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* - start - start address (may not be aligned)
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* - end - end address (exclusive, may not be aligned)
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* - flags - vma_area_struct flags describing address space
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*/
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ENTRY(v4_flush_user_cache_range)
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#ifdef CONFIG_CPU_CP15
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mov ip, #0
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mcreq p15, 0, ip, c7, c7, 0 @ flush ID cache
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mov pc, lr
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#else
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/* FALLTHROUGH */
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#endif
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/*
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* coherent_kern_range(start, end)
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*
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* Ensure coherency between the Icache and the Dcache in the
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* region described by start. If you have non-snooping
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* Harvard caches, you need to implement this function.
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*
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* - start - virtual start address
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* - end - virtual end address
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*/
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ENTRY(v4_coherent_kern_range)
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/* FALLTHROUGH */
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/*
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* coherent_user_range(start, end)
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*
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* Ensure coherency between the Icache and the Dcache in the
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* region described by start. If you have non-snooping
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* Harvard caches, you need to implement this function.
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*
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* - start - virtual start address
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* - end - virtual end address
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*/
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ENTRY(v4_coherent_user_range)
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mov r0, #0
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mov pc, lr
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/*
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* flush_kern_dcache_area(void *addr, size_t size)
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*
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* Ensure no D cache aliasing occurs, either with itself or
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* the I cache
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*
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* - addr - kernel address
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* - size - region size
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*/
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ENTRY(v4_flush_kern_dcache_area)
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/* FALLTHROUGH */
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/*
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* dma_flush_range(start, end)
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*
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* Clean and invalidate the specified virtual address range.
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*
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* - start - virtual start address
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* - end - virtual end address
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*/
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ENTRY(v4_dma_flush_range)
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#ifdef CONFIG_CPU_CP15
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mov r0, #0
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mcr p15, 0, r0, c7, c7, 0 @ flush ID cache
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#endif
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mov pc, lr
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/*
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* dma_unmap_area(start, size, dir)
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* - start - kernel virtual start address
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* - size - size of region
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* - dir - DMA direction
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*/
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ENTRY(v4_dma_unmap_area)
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teq r2, #DMA_TO_DEVICE
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bne v4_dma_flush_range
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/* FALLTHROUGH */
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/*
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* dma_map_area(start, size, dir)
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* - start - kernel virtual start address
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* - size - size of region
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* - dir - DMA direction
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*/
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ENTRY(v4_dma_map_area)
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mov pc, lr
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ENDPROC(v4_dma_unmap_area)
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ENDPROC(v4_dma_map_area)
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__INITDATA
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@ define struct cpu_cache_fns (see <asm/cacheflush.h> and proc-macros.S)
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define_cache_functions v4
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