mirror of
https://github.com/edk2-porting/linux-next.git
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1da177e4c3
Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
128 lines
3.9 KiB
C
128 lines
3.9 KiB
C
/*
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* mesh.h: definitions for the driver for the MESH SCSI bus adaptor
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* (Macintosh Enhanced SCSI Hardware) found on Power Macintosh computers.
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*
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* Copyright (C) 1996 Paul Mackerras.
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*/
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#ifndef _MESH_H
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#define _MESH_H
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/*
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* Registers in the MESH controller.
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*/
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struct mesh_regs {
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unsigned char count_lo;
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char pad0[15];
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unsigned char count_hi;
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char pad1[15];
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unsigned char fifo;
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char pad2[15];
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unsigned char sequence;
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char pad3[15];
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unsigned char bus_status0;
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char pad4[15];
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unsigned char bus_status1;
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char pad5[15];
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unsigned char fifo_count;
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char pad6[15];
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unsigned char exception;
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char pad7[15];
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unsigned char error;
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char pad8[15];
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unsigned char intr_mask;
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char pad9[15];
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unsigned char interrupt;
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char pad10[15];
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unsigned char source_id;
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char pad11[15];
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unsigned char dest_id;
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char pad12[15];
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unsigned char sync_params;
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char pad13[15];
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unsigned char mesh_id;
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char pad14[15];
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unsigned char sel_timeout;
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char pad15[15];
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};
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/* Bits in the sequence register. */
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#define SEQ_DMA_MODE 0x80 /* use DMA for data transfer */
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#define SEQ_TARGET 0x40 /* put the controller into target mode */
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#define SEQ_ATN 0x20 /* assert ATN signal */
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#define SEQ_ACTIVE_NEG 0x10 /* use active negation on REQ/ACK */
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#define SEQ_CMD 0x0f /* command bits: */
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#define SEQ_ARBITRATE 1 /* get the bus */
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#define SEQ_SELECT 2 /* select a target */
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#define SEQ_COMMAND 3 /* send a command */
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#define SEQ_STATUS 4 /* receive status */
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#define SEQ_DATAOUT 5 /* send data */
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#define SEQ_DATAIN 6 /* receive data */
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#define SEQ_MSGOUT 7 /* send a message */
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#define SEQ_MSGIN 8 /* receive a message */
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#define SEQ_BUSFREE 9 /* look for bus free */
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#define SEQ_ENBPARITY 0x0a /* enable parity checking */
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#define SEQ_DISPARITY 0x0b /* disable parity checking */
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#define SEQ_ENBRESEL 0x0c /* enable reselection */
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#define SEQ_DISRESEL 0x0d /* disable reselection */
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#define SEQ_RESETMESH 0x0e /* reset the controller */
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#define SEQ_FLUSHFIFO 0x0f /* clear out the FIFO */
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/* Bits in the bus_status0 and bus_status1 registers:
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these correspond directly to the SCSI bus control signals. */
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#define BS0_REQ 0x20
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#define BS0_ACK 0x10
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#define BS0_ATN 0x08
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#define BS0_MSG 0x04
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#define BS0_CD 0x02
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#define BS0_IO 0x01
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#define BS1_RST 0x80
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#define BS1_BSY 0x40
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#define BS1_SEL 0x20
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/* Bus phases defined by the bits in bus_status0 */
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#define BS0_PHASE (BS0_MSG+BS0_CD+BS0_IO)
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#define BP_DATAOUT 0
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#define BP_DATAIN BS0_IO
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#define BP_COMMAND BS0_CD
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#define BP_STATUS (BS0_CD+BS0_IO)
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#define BP_MSGOUT (BS0_MSG+BS0_CD)
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#define BP_MSGIN (BS0_MSG+BS0_CD+BS0_IO)
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/* Bits in the exception register. */
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#define EXC_SELWATN 0x20 /* (as target) we were selected with ATN */
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#define EXC_SELECTED 0x10 /* (as target) we were selected w/o ATN */
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#define EXC_RESELECTED 0x08 /* (as initiator) we were reselected */
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#define EXC_ARBLOST 0x04 /* we lost arbitration */
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#define EXC_PHASEMM 0x02 /* SCSI phase mismatch */
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#define EXC_SELTO 0x01 /* selection timeout */
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/* Bits in the error register */
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#define ERR_UNEXPDISC 0x40 /* target unexpectedly disconnected */
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#define ERR_SCSIRESET 0x20 /* SCSI bus got reset on us */
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#define ERR_SEQERR 0x10 /* we did something the chip didn't like */
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#define ERR_PARITY 0x01 /* parity error was detected */
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/* Bits in the interrupt and intr_mask registers */
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#define INT_ERROR 0x04 /* error interrupt */
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#define INT_EXCEPTION 0x02 /* exception interrupt */
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#define INT_CMDDONE 0x01 /* command done interrupt */
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/* Fields in the sync_params register */
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#define SYNC_OFF(x) ((x) >> 4) /* offset field */
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#define SYNC_PER(x) ((x) & 0xf) /* period field */
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#define SYNC_PARAMS(o, p) (((o) << 4) | (p))
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#define ASYNC_PARAMS 2 /* sync_params value for async xfers */
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/*
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* Assuming a clock frequency of 50MHz:
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*
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* The transfer period with SYNC_PER(sync_params) == x
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* is (x + 2) * 40ns, except that x == 0 gives 100ns.
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*
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* The units of the sel_timeout register are 10ms.
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*/
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#endif /* _MESH_H */
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