mirror of
https://github.com/edk2-porting/linux-next.git
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d41f59fd92
Added Spreadtrum's clock driver framework together with common structures and interface functions. Signed-off-by: Chunyan Zhang <chunyan.zhang@spreadtrum.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
97 lines
2.0 KiB
C
97 lines
2.0 KiB
C
// SPDX-License-Identifier: GPL-2.0
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//
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// Spreadtrum clock infrastructure
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//
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// Copyright (C) 2017 Spreadtrum, Inc.
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// Author: Chunyan Zhang <chunyan.zhang@spreadtrum.com>
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#include <linux/mfd/syscon.h>
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#include <linux/module.h>
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#include <linux/of_address.h>
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#include <linux/of_platform.h>
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#include <linux/regmap.h>
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#include "common.h"
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static const struct regmap_config sprdclk_regmap_config = {
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.reg_bits = 32,
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.reg_stride = 4,
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.val_bits = 32,
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.max_register = 0xffff,
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.fast_io = true,
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};
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static void sprd_clk_set_regmap(const struct sprd_clk_desc *desc,
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struct regmap *regmap)
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{
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int i;
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struct sprd_clk_common *cclk;
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for (i = 0; i < desc->num_clk_clks; i++) {
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cclk = desc->clk_clks[i];
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if (!cclk)
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continue;
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cclk->regmap = regmap;
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}
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}
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int sprd_clk_regmap_init(struct platform_device *pdev,
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const struct sprd_clk_desc *desc)
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{
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void __iomem *base;
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struct device_node *node = pdev->dev.of_node;
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struct regmap *regmap;
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if (of_find_property(node, "sprd,syscon", NULL)) {
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regmap = syscon_regmap_lookup_by_phandle(node, "sprd,syscon");
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if (IS_ERR_OR_NULL(regmap)) {
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pr_err("%s: failed to get syscon regmap\n", __func__);
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return PTR_ERR(regmap);
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}
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} else {
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base = of_iomap(node, 0);
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regmap = devm_regmap_init_mmio(&pdev->dev, base,
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&sprdclk_regmap_config);
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if (IS_ERR_OR_NULL(regmap)) {
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pr_err("failed to init regmap\n");
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return PTR_ERR(regmap);
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}
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}
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sprd_clk_set_regmap(desc, regmap);
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return 0;
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}
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EXPORT_SYMBOL_GPL(sprd_clk_regmap_init);
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int sprd_clk_probe(struct device *dev, struct clk_hw_onecell_data *clkhw)
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{
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int i, ret;
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struct clk_hw *hw;
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for (i = 0; i < clkhw->num; i++) {
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hw = clkhw->hws[i];
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if (!hw)
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continue;
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ret = devm_clk_hw_register(dev, hw);
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if (ret) {
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dev_err(dev, "Couldn't register clock %d - %s\n",
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i, hw->init->name);
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return ret;
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}
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}
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ret = devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, clkhw);
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if (ret)
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dev_err(dev, "Failed to add clock provider\n");
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return ret;
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}
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EXPORT_SYMBOL_GPL(sprd_clk_probe);
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MODULE_LICENSE("GPL v2");
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