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d330615b90
In the original driver it is missed to setup a free running driver. This timer is needed for the scheduler. So setup it. Signed-off-by: Hans Ulli Kroll <ulli.kroll@googlemail.com> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Olof Johansson <olof@lixom.net>
240 lines
6.2 KiB
C
240 lines
6.2 KiB
C
/*
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* Copyright (C) 2001-2006 Storlink, Corp.
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* Copyright (C) 2008-2009 Paulius Zaleckas <paulius.zaleckas@teltonika.lt>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*/
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#include <linux/interrupt.h>
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#include <linux/irq.h>
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#include <linux/io.h>
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#include <mach/hardware.h>
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#include <mach/global_reg.h>
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#include <asm/mach/time.h>
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#include <linux/clockchips.h>
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#include <linux/clocksource.h>
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#include <linux/sched_clock.h>
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/*
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* Register definitions for the timers
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*/
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#define TIMER1_BASE GEMINI_TIMER_BASE
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#define TIMER2_BASE (GEMINI_TIMER_BASE + 0x10)
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#define TIMER3_BASE (GEMINI_TIMER_BASE + 0x20)
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#define TIMER_COUNT(BASE) (IO_ADDRESS(BASE) + 0x00)
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#define TIMER_LOAD(BASE) (IO_ADDRESS(BASE) + 0x04)
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#define TIMER_MATCH1(BASE) (IO_ADDRESS(BASE) + 0x08)
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#define TIMER_MATCH2(BASE) (IO_ADDRESS(BASE) + 0x0C)
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#define TIMER_CR (IO_ADDRESS(GEMINI_TIMER_BASE) + 0x30)
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#define TIMER_INTR_STATE (IO_ADDRESS(GEMINI_TIMER_BASE) + 0x34)
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#define TIMER_INTR_MASK (IO_ADDRESS(GEMINI_TIMER_BASE) + 0x38)
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#define TIMER_1_CR_ENABLE (1 << 0)
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#define TIMER_1_CR_CLOCK (1 << 1)
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#define TIMER_1_CR_INT (1 << 2)
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#define TIMER_2_CR_ENABLE (1 << 3)
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#define TIMER_2_CR_CLOCK (1 << 4)
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#define TIMER_2_CR_INT (1 << 5)
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#define TIMER_3_CR_ENABLE (1 << 6)
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#define TIMER_3_CR_CLOCK (1 << 7)
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#define TIMER_3_CR_INT (1 << 8)
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#define TIMER_1_CR_UPDOWN (1 << 9)
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#define TIMER_2_CR_UPDOWN (1 << 10)
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#define TIMER_3_CR_UPDOWN (1 << 11)
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#define TIMER_DEFAULT_FLAGS (TIMER_1_CR_UPDOWN | \
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TIMER_3_CR_ENABLE | \
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TIMER_3_CR_UPDOWN)
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#define TIMER_1_INT_MATCH1 (1 << 0)
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#define TIMER_1_INT_MATCH2 (1 << 1)
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#define TIMER_1_INT_OVERFLOW (1 << 2)
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#define TIMER_2_INT_MATCH1 (1 << 3)
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#define TIMER_2_INT_MATCH2 (1 << 4)
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#define TIMER_2_INT_OVERFLOW (1 << 5)
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#define TIMER_3_INT_MATCH1 (1 << 6)
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#define TIMER_3_INT_MATCH2 (1 << 7)
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#define TIMER_3_INT_OVERFLOW (1 << 8)
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#define TIMER_INT_ALL_MASK 0x1ff
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static unsigned int tick_rate;
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static u64 notrace gemini_read_sched_clock(void)
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{
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return readl(TIMER_COUNT(TIMER3_BASE));
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}
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static int gemini_timer_set_next_event(unsigned long cycles,
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struct clock_event_device *evt)
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{
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u32 cr;
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/* Setup the match register */
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cr = readl(TIMER_COUNT(TIMER1_BASE));
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writel(cr + cycles, TIMER_MATCH1(TIMER1_BASE));
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if (readl(TIMER_COUNT(TIMER1_BASE)) - cr > cycles)
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return -ETIME;
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return 0;
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}
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static int gemini_timer_shutdown(struct clock_event_device *evt)
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{
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u32 cr;
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/*
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* Disable also for oneshot: the set_next() call will arm the timer
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* instead.
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*/
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/* Stop timer and interrupt. */
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cr = readl(TIMER_CR);
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cr &= ~(TIMER_1_CR_ENABLE | TIMER_1_CR_INT);
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writel(cr, TIMER_CR);
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/* Setup counter start from 0 */
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writel(0, TIMER_COUNT(TIMER1_BASE));
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writel(0, TIMER_LOAD(TIMER1_BASE));
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/* enable interrupt */
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cr = readl(TIMER_INTR_MASK);
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cr &= ~(TIMER_1_INT_OVERFLOW | TIMER_1_INT_MATCH2);
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cr |= TIMER_1_INT_MATCH1;
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writel(cr, TIMER_INTR_MASK);
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/* start the timer */
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cr = readl(TIMER_CR);
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cr |= TIMER_1_CR_ENABLE;
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writel(cr, TIMER_CR);
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return 0;
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}
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static int gemini_timer_set_periodic(struct clock_event_device *evt)
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{
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u32 period = DIV_ROUND_CLOSEST(tick_rate, HZ);
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u32 cr;
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/* Stop timer and interrupt */
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cr = readl(TIMER_CR);
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cr &= ~(TIMER_1_CR_ENABLE | TIMER_1_CR_INT);
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writel(cr, TIMER_CR);
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/* Setup timer to fire at 1/HT intervals. */
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cr = 0xffffffff - (period - 1);
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writel(cr, TIMER_COUNT(TIMER1_BASE));
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writel(cr, TIMER_LOAD(TIMER1_BASE));
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/* enable interrupt on overflow */
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cr = readl(TIMER_INTR_MASK);
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cr &= ~(TIMER_1_INT_MATCH1 | TIMER_1_INT_MATCH2);
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cr |= TIMER_1_INT_OVERFLOW;
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writel(cr, TIMER_INTR_MASK);
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/* Start the timer */
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cr = readl(TIMER_CR);
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cr |= TIMER_1_CR_ENABLE;
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cr |= TIMER_1_CR_INT;
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writel(cr, TIMER_CR);
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return 0;
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}
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/* Use TIMER1 as clock event */
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static struct clock_event_device gemini_clockevent = {
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.name = "TIMER1",
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/* Reasonably fast and accurate clock event */
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.rating = 300,
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.shift = 32,
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.features = CLOCK_EVT_FEAT_PERIODIC |
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CLOCK_EVT_FEAT_ONESHOT,
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.set_next_event = gemini_timer_set_next_event,
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.set_state_shutdown = gemini_timer_shutdown,
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.set_state_periodic = gemini_timer_set_periodic,
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.set_state_oneshot = gemini_timer_shutdown,
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.tick_resume = gemini_timer_shutdown,
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};
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/*
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* IRQ handler for the timer
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*/
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static irqreturn_t gemini_timer_interrupt(int irq, void *dev_id)
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{
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struct clock_event_device *evt = &gemini_clockevent;
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evt->event_handler(evt);
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return IRQ_HANDLED;
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}
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static struct irqaction gemini_timer_irq = {
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.name = "Gemini Timer Tick",
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.flags = IRQF_TIMER,
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.handler = gemini_timer_interrupt,
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};
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/*
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* Set up timer interrupt, and return the current time in seconds.
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*/
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void __init gemini_timer_init(void)
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{
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u32 reg_v;
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reg_v = readl(IO_ADDRESS(GEMINI_GLOBAL_BASE + GLOBAL_STATUS));
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tick_rate = REG_TO_AHB_SPEED(reg_v) * 1000000;
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printk(KERN_INFO "Bus: %dMHz", tick_rate / 1000000);
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tick_rate /= 6; /* APB bus run AHB*(1/6) */
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switch(reg_v & CPU_AHB_RATIO_MASK) {
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case CPU_AHB_1_1:
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printk(KERN_CONT "(1/1)\n");
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break;
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case CPU_AHB_3_2:
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printk(KERN_CONT "(3/2)\n");
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break;
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case CPU_AHB_24_13:
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printk(KERN_CONT "(24/13)\n");
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break;
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case CPU_AHB_2_1:
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printk(KERN_CONT "(2/1)\n");
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break;
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}
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/*
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* Reset the interrupt mask and status
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*/
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writel(TIMER_INT_ALL_MASK, TIMER_INTR_MASK);
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writel(0, TIMER_INTR_STATE);
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writel(TIMER_DEFAULT_FLAGS, TIMER_CR);
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/*
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* Setup free-running clocksource timer (interrupts
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* disabled.)
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*/
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writel(0, TIMER_COUNT(TIMER3_BASE));
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writel(0, TIMER_LOAD(TIMER3_BASE));
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writel(0, TIMER_MATCH1(TIMER3_BASE));
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writel(0, TIMER_MATCH2(TIMER3_BASE));
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clocksource_mmio_init(TIMER_COUNT(TIMER3_BASE),
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"gemini_clocksource", tick_rate,
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300, 32, clocksource_mmio_readl_up);
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sched_clock_register(gemini_read_sched_clock, 32, tick_rate);
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/*
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* Setup clockevent timer (interrupt-driven.)
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*/
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writel(0, TIMER_COUNT(TIMER1_BASE));
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writel(0, TIMER_LOAD(TIMER1_BASE));
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writel(0, TIMER_MATCH1(TIMER1_BASE));
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writel(0, TIMER_MATCH2(TIMER1_BASE));
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setup_irq(IRQ_TIMER1, &gemini_timer_irq);
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gemini_clockevent.cpumask = cpumask_of(0);
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clockevents_config_and_register(&gemini_clockevent, tick_rate,
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1, 0xffffffff);
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}
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