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https://github.com/edk2-porting/linux-next.git
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d0a57bd5b5
tegra_clocks_apply_init_table() needs to be called after the udelay
loop has been calibrated (see commit
441f199a37 ("clk: tegra: defer
application of init table") for why that is). On existing Tegra SoCs
this was done by calling tegra_clocks_apply_init_table() from
tegra_dt_init(). To make this also work on ARM64, we need to change
this into an initcall. tegra_dt_init() is called from
customize_machine which is an arch_initcall. Therefore this should
also work on existing 32bit Tegra SoCs.
Tested on Tegra20 (ventana), Tegra30 (beaverboard), Tegra124 (jetson TK1) and
Tegra132.
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
[paul@pwsan.com: tweaked the commit message]
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Paul Walmsley <pwalmsley@nvidia.com>
Cc: Thierry Reding <treding@nvidia.com>
Cc: Prashant Gaikwad <pgaikwad@nvidia.com>
Cc: Mike Turquette <mturquette@linaro.org>
Cc: Stephen Boyd <sboyd@codeaurora.org>
Cc: Stephen Warren <swarren@wwwdotorg.org>
Cc: Thierry Reding <thierry.reding@gmail.com>
Cc: Alexandre Courbot <gnurou@gmail.com>
124 lines
2.8 KiB
C
124 lines
2.8 KiB
C
/*
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* Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef __LINUX_CLK_TEGRA_H_
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#define __LINUX_CLK_TEGRA_H_
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#include <linux/clk.h>
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/*
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* Tegra CPU clock and reset control ops
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*
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* wait_for_reset:
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* keep waiting until the CPU in reset state
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* put_in_reset:
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* put the CPU in reset state
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* out_of_reset:
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* release the CPU from reset state
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* enable_clock:
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* CPU clock un-gate
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* disable_clock:
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* CPU clock gate
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* rail_off_ready:
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* CPU is ready for rail off
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* suspend:
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* save the clock settings when CPU go into low-power state
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* resume:
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* restore the clock settings when CPU exit low-power state
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*/
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struct tegra_cpu_car_ops {
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void (*wait_for_reset)(u32 cpu);
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void (*put_in_reset)(u32 cpu);
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void (*out_of_reset)(u32 cpu);
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void (*enable_clock)(u32 cpu);
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void (*disable_clock)(u32 cpu);
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#ifdef CONFIG_PM_SLEEP
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bool (*rail_off_ready)(void);
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void (*suspend)(void);
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void (*resume)(void);
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#endif
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};
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extern struct tegra_cpu_car_ops *tegra_cpu_car_ops;
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static inline void tegra_wait_cpu_in_reset(u32 cpu)
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{
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if (WARN_ON(!tegra_cpu_car_ops->wait_for_reset))
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return;
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tegra_cpu_car_ops->wait_for_reset(cpu);
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}
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static inline void tegra_put_cpu_in_reset(u32 cpu)
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{
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if (WARN_ON(!tegra_cpu_car_ops->put_in_reset))
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return;
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tegra_cpu_car_ops->put_in_reset(cpu);
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}
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static inline void tegra_cpu_out_of_reset(u32 cpu)
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{
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if (WARN_ON(!tegra_cpu_car_ops->out_of_reset))
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return;
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tegra_cpu_car_ops->out_of_reset(cpu);
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}
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static inline void tegra_enable_cpu_clock(u32 cpu)
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{
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if (WARN_ON(!tegra_cpu_car_ops->enable_clock))
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return;
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tegra_cpu_car_ops->enable_clock(cpu);
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}
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static inline void tegra_disable_cpu_clock(u32 cpu)
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{
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if (WARN_ON(!tegra_cpu_car_ops->disable_clock))
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return;
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tegra_cpu_car_ops->disable_clock(cpu);
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}
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#ifdef CONFIG_PM_SLEEP
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static inline bool tegra_cpu_rail_off_ready(void)
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{
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if (WARN_ON(!tegra_cpu_car_ops->rail_off_ready))
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return false;
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return tegra_cpu_car_ops->rail_off_ready();
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}
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static inline void tegra_cpu_clock_suspend(void)
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{
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if (WARN_ON(!tegra_cpu_car_ops->suspend))
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return;
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tegra_cpu_car_ops->suspend();
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}
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static inline void tegra_cpu_clock_resume(void)
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{
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if (WARN_ON(!tegra_cpu_car_ops->resume))
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return;
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tegra_cpu_car_ops->resume();
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}
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#endif
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#endif /* __LINUX_CLK_TEGRA_H_ */
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