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55b8fd4f42
All SPEAr SoC's contain PLLs. Their Fout is derived based on following equations - In normal mode vco = (2 * M[15:8] * Fin)/N - In Dithered mode vco = (2 * M[15:0] * Fin)/(256 * N) pll_rate = vco/2^p vco and pll are very closely bound to each other, "vco needs to program: mode, m & n" and "pll needs to program p", both share common enable/disable logic and registers. This patch adds in support for this type of clock. Signed-off-by: Viresh Kumar <viresh.kumar@st.com> Reviewed-by: Mike Turquette <mturquette@linaro.org>
59 lines
1.4 KiB
C
59 lines
1.4 KiB
C
/*
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* Clock framework definitions for SPEAr platform
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*
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* Copyright (C) 2012 ST Microelectronics
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* Viresh Kumar <viresh.kumar@st.com>
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#ifndef __SPEAR_CLK_H
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#define __SPEAR_CLK_H
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#include <linux/clk-provider.h>
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#include <linux/spinlock_types.h>
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#include <linux/types.h>
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/* VCO-PLL clk */
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struct pll_rate_tbl {
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u8 mode;
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u16 m;
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u8 n;
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u8 p;
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};
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struct clk_vco {
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struct clk_hw hw;
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void __iomem *mode_reg;
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void __iomem *cfg_reg;
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struct pll_rate_tbl *rtbl;
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u8 rtbl_cnt;
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spinlock_t *lock;
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};
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struct clk_pll {
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struct clk_hw hw;
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struct clk_vco *vco;
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const char *parent[1];
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spinlock_t *lock;
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};
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typedef unsigned long (*clk_calc_rate)(struct clk_hw *hw, unsigned long prate,
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int index);
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/* clk register routines */
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struct clk *clk_register_vco_pll(const char *vco_name, const char *pll_name,
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const char *vco_gate_name, const char *parent_name,
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unsigned long flags, void __iomem *mode_reg, void __iomem
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*cfg_reg, struct pll_rate_tbl *rtbl, u8 rtbl_cnt,
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spinlock_t *lock, struct clk **pll_clk,
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struct clk **vco_gate_clk);
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long clk_round_rate_index(struct clk_hw *hw, unsigned long drate,
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unsigned long parent_rate, clk_calc_rate calc_rate, u8 rtbl_cnt,
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int *index);
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#endif /* __SPEAR_CLK_H */
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