mirror of
https://github.com/edk2-porting/linux-next.git
synced 2024-12-23 12:43:55 +08:00
0fc0b732ea
No need to put ethtool_ops in data, they should be const. Signed-off-by: Stephen Hemminger <shemminger@vyatta.com> Signed-off-by: David S. Miller <davem@davemloft.net>
1215 lines
28 KiB
C
1215 lines
28 KiB
C
/*
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* Blackfin On-Chip MAC Driver
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*
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* Copyright 2004-2007 Analog Devices Inc.
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*
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* Enter bugs at http://blackfin.uclinux.org/
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*
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* Licensed under the GPL-2 or later.
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*/
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#include <linux/init.h>
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <linux/sched.h>
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#include <linux/slab.h>
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#include <linux/delay.h>
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#include <linux/timer.h>
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#include <linux/errno.h>
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#include <linux/irq.h>
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#include <linux/io.h>
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#include <linux/ioport.h>
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#include <linux/crc32.h>
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#include <linux/device.h>
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#include <linux/spinlock.h>
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#include <linux/mii.h>
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#include <linux/phy.h>
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#include <linux/netdevice.h>
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#include <linux/etherdevice.h>
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#include <linux/ethtool.h>
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#include <linux/skbuff.h>
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#include <linux/platform_device.h>
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#include <asm/dma.h>
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#include <linux/dma-mapping.h>
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#include <asm/blackfin.h>
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#include <asm/cacheflush.h>
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#include <asm/portmux.h>
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#include "bfin_mac.h"
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#define DRV_NAME "bfin_mac"
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#define DRV_VERSION "1.1"
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#define DRV_AUTHOR "Bryan Wu, Luke Yang"
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#define DRV_DESC "Blackfin on-chip Ethernet MAC driver"
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MODULE_AUTHOR(DRV_AUTHOR);
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MODULE_LICENSE("GPL");
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MODULE_DESCRIPTION(DRV_DESC);
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MODULE_ALIAS("platform:bfin_mac");
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#if defined(CONFIG_BFIN_MAC_USE_L1)
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# define bfin_mac_alloc(dma_handle, size) l1_data_sram_zalloc(size)
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# define bfin_mac_free(dma_handle, ptr) l1_data_sram_free(ptr)
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#else
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# define bfin_mac_alloc(dma_handle, size) \
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dma_alloc_coherent(NULL, size, dma_handle, GFP_KERNEL)
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# define bfin_mac_free(dma_handle, ptr) \
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dma_free_coherent(NULL, sizeof(*ptr), ptr, dma_handle)
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#endif
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#define PKT_BUF_SZ 1580
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#define MAX_TIMEOUT_CNT 500
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/* pointers to maintain transmit list */
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static struct net_dma_desc_tx *tx_list_head;
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static struct net_dma_desc_tx *tx_list_tail;
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static struct net_dma_desc_rx *rx_list_head;
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static struct net_dma_desc_rx *rx_list_tail;
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static struct net_dma_desc_rx *current_rx_ptr;
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static struct net_dma_desc_tx *current_tx_ptr;
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static struct net_dma_desc_tx *tx_desc;
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static struct net_dma_desc_rx *rx_desc;
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#if defined(CONFIG_BFIN_MAC_RMII)
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static u16 pin_req[] = P_RMII0;
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#else
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static u16 pin_req[] = P_MII0;
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#endif
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static void bfin_mac_disable(void);
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static void bfin_mac_enable(void);
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static void desc_list_free(void)
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{
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struct net_dma_desc_rx *r;
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struct net_dma_desc_tx *t;
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int i;
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#if !defined(CONFIG_BFIN_MAC_USE_L1)
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dma_addr_t dma_handle = 0;
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#endif
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if (tx_desc) {
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t = tx_list_head;
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for (i = 0; i < CONFIG_BFIN_TX_DESC_NUM; i++) {
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if (t) {
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if (t->skb) {
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dev_kfree_skb(t->skb);
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t->skb = NULL;
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}
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t = t->next;
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}
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}
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bfin_mac_free(dma_handle, tx_desc);
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}
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if (rx_desc) {
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r = rx_list_head;
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for (i = 0; i < CONFIG_BFIN_RX_DESC_NUM; i++) {
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if (r) {
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if (r->skb) {
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dev_kfree_skb(r->skb);
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r->skb = NULL;
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}
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r = r->next;
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}
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}
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bfin_mac_free(dma_handle, rx_desc);
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}
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}
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static int desc_list_init(void)
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{
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int i;
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struct sk_buff *new_skb;
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#if !defined(CONFIG_BFIN_MAC_USE_L1)
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/*
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* This dma_handle is useless in Blackfin dma_alloc_coherent().
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* The real dma handler is the return value of dma_alloc_coherent().
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*/
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dma_addr_t dma_handle;
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#endif
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tx_desc = bfin_mac_alloc(&dma_handle,
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sizeof(struct net_dma_desc_tx) *
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CONFIG_BFIN_TX_DESC_NUM);
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if (tx_desc == NULL)
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goto init_error;
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rx_desc = bfin_mac_alloc(&dma_handle,
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sizeof(struct net_dma_desc_rx) *
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CONFIG_BFIN_RX_DESC_NUM);
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if (rx_desc == NULL)
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goto init_error;
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/* init tx_list */
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tx_list_head = tx_list_tail = tx_desc;
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for (i = 0; i < CONFIG_BFIN_TX_DESC_NUM; i++) {
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struct net_dma_desc_tx *t = tx_desc + i;
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struct dma_descriptor *a = &(t->desc_a);
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struct dma_descriptor *b = &(t->desc_b);
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/*
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* disable DMA
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* read from memory WNR = 0
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* wordsize is 32 bits
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* 6 half words is desc size
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* large desc flow
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*/
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a->config = WDSIZE_32 | NDSIZE_6 | DMAFLOW_LARGE;
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a->start_addr = (unsigned long)t->packet;
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a->x_count = 0;
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a->next_dma_desc = b;
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/*
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* enabled DMA
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* write to memory WNR = 1
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* wordsize is 32 bits
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* disable interrupt
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* 6 half words is desc size
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* large desc flow
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*/
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b->config = DMAEN | WNR | WDSIZE_32 | NDSIZE_6 | DMAFLOW_LARGE;
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b->start_addr = (unsigned long)(&(t->status));
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b->x_count = 0;
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t->skb = NULL;
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tx_list_tail->desc_b.next_dma_desc = a;
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tx_list_tail->next = t;
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tx_list_tail = t;
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}
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tx_list_tail->next = tx_list_head; /* tx_list is a circle */
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tx_list_tail->desc_b.next_dma_desc = &(tx_list_head->desc_a);
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current_tx_ptr = tx_list_head;
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/* init rx_list */
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rx_list_head = rx_list_tail = rx_desc;
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for (i = 0; i < CONFIG_BFIN_RX_DESC_NUM; i++) {
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struct net_dma_desc_rx *r = rx_desc + i;
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struct dma_descriptor *a = &(r->desc_a);
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struct dma_descriptor *b = &(r->desc_b);
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/* allocate a new skb for next time receive */
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new_skb = dev_alloc_skb(PKT_BUF_SZ + NET_IP_ALIGN);
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if (!new_skb) {
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printk(KERN_NOTICE DRV_NAME
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": init: low on mem - packet dropped\n");
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goto init_error;
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}
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skb_reserve(new_skb, NET_IP_ALIGN);
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r->skb = new_skb;
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/*
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* enabled DMA
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* write to memory WNR = 1
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* wordsize is 32 bits
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* disable interrupt
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* 6 half words is desc size
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* large desc flow
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*/
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a->config = DMAEN | WNR | WDSIZE_32 | NDSIZE_6 | DMAFLOW_LARGE;
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/* since RXDWA is enabled */
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a->start_addr = (unsigned long)new_skb->data - 2;
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a->x_count = 0;
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a->next_dma_desc = b;
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/*
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* enabled DMA
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* write to memory WNR = 1
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* wordsize is 32 bits
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* enable interrupt
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* 6 half words is desc size
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* large desc flow
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*/
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b->config = DMAEN | WNR | WDSIZE_32 | DI_EN |
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NDSIZE_6 | DMAFLOW_LARGE;
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b->start_addr = (unsigned long)(&(r->status));
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b->x_count = 0;
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rx_list_tail->desc_b.next_dma_desc = a;
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rx_list_tail->next = r;
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rx_list_tail = r;
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}
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rx_list_tail->next = rx_list_head; /* rx_list is a circle */
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rx_list_tail->desc_b.next_dma_desc = &(rx_list_head->desc_a);
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current_rx_ptr = rx_list_head;
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return 0;
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init_error:
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desc_list_free();
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printk(KERN_ERR DRV_NAME ": kmalloc failed\n");
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return -ENOMEM;
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}
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/*---PHY CONTROL AND CONFIGURATION-----------------------------------------*/
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/*
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* MII operations
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*/
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/* Wait until the previous MDC/MDIO transaction has completed */
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static void bfin_mdio_poll(void)
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{
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int timeout_cnt = MAX_TIMEOUT_CNT;
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/* poll the STABUSY bit */
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while ((bfin_read_EMAC_STAADD()) & STABUSY) {
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udelay(1);
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if (timeout_cnt-- < 0) {
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printk(KERN_ERR DRV_NAME
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": wait MDC/MDIO transaction to complete timeout\n");
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break;
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}
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}
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}
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/* Read an off-chip register in a PHY through the MDC/MDIO port */
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static int bfin_mdiobus_read(struct mii_bus *bus, int phy_addr, int regnum)
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{
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bfin_mdio_poll();
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/* read mode */
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bfin_write_EMAC_STAADD(SET_PHYAD((u16) phy_addr) |
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SET_REGAD((u16) regnum) |
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STABUSY);
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bfin_mdio_poll();
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return (int) bfin_read_EMAC_STADAT();
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}
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/* Write an off-chip register in a PHY through the MDC/MDIO port */
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static int bfin_mdiobus_write(struct mii_bus *bus, int phy_addr, int regnum,
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u16 value)
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{
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bfin_mdio_poll();
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bfin_write_EMAC_STADAT((u32) value);
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/* write mode */
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bfin_write_EMAC_STAADD(SET_PHYAD((u16) phy_addr) |
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SET_REGAD((u16) regnum) |
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STAOP |
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STABUSY);
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bfin_mdio_poll();
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return 0;
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}
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static int bfin_mdiobus_reset(struct mii_bus *bus)
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{
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return 0;
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}
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static void bfin_mac_adjust_link(struct net_device *dev)
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{
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struct bfin_mac_local *lp = netdev_priv(dev);
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struct phy_device *phydev = lp->phydev;
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unsigned long flags;
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int new_state = 0;
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spin_lock_irqsave(&lp->lock, flags);
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if (phydev->link) {
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/* Now we make sure that we can be in full duplex mode.
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* If not, we operate in half-duplex mode. */
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if (phydev->duplex != lp->old_duplex) {
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u32 opmode = bfin_read_EMAC_OPMODE();
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new_state = 1;
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if (phydev->duplex)
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opmode |= FDMODE;
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else
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opmode &= ~(FDMODE);
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bfin_write_EMAC_OPMODE(opmode);
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lp->old_duplex = phydev->duplex;
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}
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if (phydev->speed != lp->old_speed) {
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#if defined(CONFIG_BFIN_MAC_RMII)
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u32 opmode = bfin_read_EMAC_OPMODE();
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switch (phydev->speed) {
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case 10:
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opmode |= RMII_10;
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break;
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case 100:
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opmode &= ~(RMII_10);
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break;
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default:
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printk(KERN_WARNING
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"%s: Ack! Speed (%d) is not 10/100!\n",
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DRV_NAME, phydev->speed);
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break;
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}
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bfin_write_EMAC_OPMODE(opmode);
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#endif
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new_state = 1;
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lp->old_speed = phydev->speed;
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}
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if (!lp->old_link) {
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new_state = 1;
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lp->old_link = 1;
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}
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} else if (lp->old_link) {
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new_state = 1;
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lp->old_link = 0;
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lp->old_speed = 0;
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lp->old_duplex = -1;
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}
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if (new_state) {
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u32 opmode = bfin_read_EMAC_OPMODE();
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phy_print_status(phydev);
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pr_debug("EMAC_OPMODE = 0x%08x\n", opmode);
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}
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spin_unlock_irqrestore(&lp->lock, flags);
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}
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/* MDC = 2.5 MHz */
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#define MDC_CLK 2500000
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static int mii_probe(struct net_device *dev)
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{
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struct bfin_mac_local *lp = netdev_priv(dev);
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struct phy_device *phydev = NULL;
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unsigned short sysctl;
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int i;
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u32 sclk, mdc_div;
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/* Enable PHY output early */
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if (!(bfin_read_VR_CTL() & PHYCLKOE))
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bfin_write_VR_CTL(bfin_read_VR_CTL() | PHYCLKOE);
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sclk = get_sclk();
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mdc_div = ((sclk / MDC_CLK) / 2) - 1;
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sysctl = bfin_read_EMAC_SYSCTL();
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sysctl = (sysctl & ~MDCDIV) | SET_MDCDIV(mdc_div);
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bfin_write_EMAC_SYSCTL(sysctl);
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/* search for connect PHY device */
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for (i = 0; i < PHY_MAX_ADDR; i++) {
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struct phy_device *const tmp_phydev = lp->mii_bus->phy_map[i];
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if (!tmp_phydev)
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continue; /* no PHY here... */
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phydev = tmp_phydev;
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break; /* found it */
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}
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/* now we are supposed to have a proper phydev, to attach to... */
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if (!phydev) {
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printk(KERN_INFO "%s: Don't found any phy device at all\n",
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dev->name);
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return -ENODEV;
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}
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#if defined(CONFIG_BFIN_MAC_RMII)
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phydev = phy_connect(dev, dev_name(&phydev->dev), &bfin_mac_adjust_link,
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0, PHY_INTERFACE_MODE_RMII);
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#else
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phydev = phy_connect(dev, dev_name(&phydev->dev), &bfin_mac_adjust_link,
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0, PHY_INTERFACE_MODE_MII);
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#endif
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if (IS_ERR(phydev)) {
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printk(KERN_ERR "%s: Could not attach to PHY\n", dev->name);
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return PTR_ERR(phydev);
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}
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/* mask with MAC supported features */
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phydev->supported &= (SUPPORTED_10baseT_Half
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| SUPPORTED_10baseT_Full
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| SUPPORTED_100baseT_Half
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| SUPPORTED_100baseT_Full
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| SUPPORTED_Autoneg
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| SUPPORTED_Pause | SUPPORTED_Asym_Pause
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| SUPPORTED_MII
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| SUPPORTED_TP);
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phydev->advertising = phydev->supported;
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lp->old_link = 0;
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lp->old_speed = 0;
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lp->old_duplex = -1;
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lp->phydev = phydev;
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printk(KERN_INFO "%s: attached PHY driver [%s] "
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"(mii_bus:phy_addr=%s, irq=%d, mdc_clk=%dHz(mdc_div=%d)"
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"@sclk=%dMHz)\n",
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DRV_NAME, phydev->drv->name, dev_name(&phydev->dev), phydev->irq,
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MDC_CLK, mdc_div, sclk/1000000);
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return 0;
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}
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/*
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* Ethtool support
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*/
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static int
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bfin_mac_ethtool_getsettings(struct net_device *dev, struct ethtool_cmd *cmd)
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{
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struct bfin_mac_local *lp = netdev_priv(dev);
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if (lp->phydev)
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return phy_ethtool_gset(lp->phydev, cmd);
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return -EINVAL;
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}
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static int
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bfin_mac_ethtool_setsettings(struct net_device *dev, struct ethtool_cmd *cmd)
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{
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struct bfin_mac_local *lp = netdev_priv(dev);
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if (!capable(CAP_NET_ADMIN))
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return -EPERM;
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if (lp->phydev)
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return phy_ethtool_sset(lp->phydev, cmd);
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return -EINVAL;
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}
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static void bfin_mac_ethtool_getdrvinfo(struct net_device *dev,
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struct ethtool_drvinfo *info)
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{
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strcpy(info->driver, DRV_NAME);
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strcpy(info->version, DRV_VERSION);
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strcpy(info->fw_version, "N/A");
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strcpy(info->bus_info, dev_name(&dev->dev));
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}
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static const struct ethtool_ops bfin_mac_ethtool_ops = {
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.get_settings = bfin_mac_ethtool_getsettings,
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.set_settings = bfin_mac_ethtool_setsettings,
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.get_link = ethtool_op_get_link,
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.get_drvinfo = bfin_mac_ethtool_getdrvinfo,
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};
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|
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/**************************************************************************/
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void setup_system_regs(struct net_device *dev)
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{
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unsigned short sysctl;
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|
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/*
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* Odd word alignment for Receive Frame DMA word
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* Configure checksum support and rcve frame word alignment
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*/
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sysctl = bfin_read_EMAC_SYSCTL();
|
|
#if defined(BFIN_MAC_CSUM_OFFLOAD)
|
|
sysctl |= RXDWA | RXCKS;
|
|
#else
|
|
sysctl |= RXDWA;
|
|
#endif
|
|
bfin_write_EMAC_SYSCTL(sysctl);
|
|
|
|
bfin_write_EMAC_MMC_CTL(RSTC | CROLL);
|
|
|
|
/* Initialize the TX DMA channel registers */
|
|
bfin_write_DMA2_X_COUNT(0);
|
|
bfin_write_DMA2_X_MODIFY(4);
|
|
bfin_write_DMA2_Y_COUNT(0);
|
|
bfin_write_DMA2_Y_MODIFY(0);
|
|
|
|
/* Initialize the RX DMA channel registers */
|
|
bfin_write_DMA1_X_COUNT(0);
|
|
bfin_write_DMA1_X_MODIFY(4);
|
|
bfin_write_DMA1_Y_COUNT(0);
|
|
bfin_write_DMA1_Y_MODIFY(0);
|
|
}
|
|
|
|
static void setup_mac_addr(u8 *mac_addr)
|
|
{
|
|
u32 addr_low = le32_to_cpu(*(__le32 *) & mac_addr[0]);
|
|
u16 addr_hi = le16_to_cpu(*(__le16 *) & mac_addr[4]);
|
|
|
|
/* this depends on a little-endian machine */
|
|
bfin_write_EMAC_ADDRLO(addr_low);
|
|
bfin_write_EMAC_ADDRHI(addr_hi);
|
|
}
|
|
|
|
static int bfin_mac_set_mac_address(struct net_device *dev, void *p)
|
|
{
|
|
struct sockaddr *addr = p;
|
|
if (netif_running(dev))
|
|
return -EBUSY;
|
|
memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
|
|
setup_mac_addr(dev->dev_addr);
|
|
return 0;
|
|
}
|
|
|
|
static void adjust_tx_list(void)
|
|
{
|
|
int timeout_cnt = MAX_TIMEOUT_CNT;
|
|
|
|
if (tx_list_head->status.status_word != 0
|
|
&& current_tx_ptr != tx_list_head) {
|
|
goto adjust_head; /* released something, just return; */
|
|
}
|
|
|
|
/*
|
|
* if nothing released, check wait condition
|
|
* current's next can not be the head,
|
|
* otherwise the dma will not stop as we want
|
|
*/
|
|
if (current_tx_ptr->next->next == tx_list_head) {
|
|
while (tx_list_head->status.status_word == 0) {
|
|
udelay(10);
|
|
if (tx_list_head->status.status_word != 0
|
|
|| !(bfin_read_DMA2_IRQ_STATUS() & DMA_RUN)) {
|
|
goto adjust_head;
|
|
}
|
|
if (timeout_cnt-- < 0) {
|
|
printk(KERN_ERR DRV_NAME
|
|
": wait for adjust tx list head timeout\n");
|
|
break;
|
|
}
|
|
}
|
|
if (tx_list_head->status.status_word != 0) {
|
|
goto adjust_head;
|
|
}
|
|
}
|
|
|
|
return;
|
|
|
|
adjust_head:
|
|
do {
|
|
tx_list_head->desc_a.config &= ~DMAEN;
|
|
tx_list_head->status.status_word = 0;
|
|
if (tx_list_head->skb) {
|
|
dev_kfree_skb(tx_list_head->skb);
|
|
tx_list_head->skb = NULL;
|
|
} else {
|
|
printk(KERN_ERR DRV_NAME
|
|
": no sk_buff in a transmitted frame!\n");
|
|
}
|
|
tx_list_head = tx_list_head->next;
|
|
} while (tx_list_head->status.status_word != 0
|
|
&& current_tx_ptr != tx_list_head);
|
|
return;
|
|
|
|
}
|
|
|
|
static int bfin_mac_hard_start_xmit(struct sk_buff *skb,
|
|
struct net_device *dev)
|
|
{
|
|
u16 *data;
|
|
u32 data_align = (unsigned long)(skb->data) & 0x3;
|
|
current_tx_ptr->skb = skb;
|
|
|
|
if (data_align == 0x2) {
|
|
/* move skb->data to current_tx_ptr payload */
|
|
data = (u16 *)(skb->data) - 1;
|
|
*data = (u16)(skb->len);
|
|
current_tx_ptr->desc_a.start_addr = (u32)data;
|
|
/* this is important! */
|
|
blackfin_dcache_flush_range((u32)data,
|
|
(u32)((u8 *)data + skb->len + 4));
|
|
} else {
|
|
*((u16 *)(current_tx_ptr->packet)) = (u16)(skb->len);
|
|
memcpy((u8 *)(current_tx_ptr->packet + 2), skb->data,
|
|
skb->len);
|
|
current_tx_ptr->desc_a.start_addr =
|
|
(u32)current_tx_ptr->packet;
|
|
if (current_tx_ptr->status.status_word != 0)
|
|
current_tx_ptr->status.status_word = 0;
|
|
blackfin_dcache_flush_range(
|
|
(u32)current_tx_ptr->packet,
|
|
(u32)(current_tx_ptr->packet + skb->len + 2));
|
|
}
|
|
|
|
/* make sure the internal data buffers in the core are drained
|
|
* so that the DMA descriptors are completely written when the
|
|
* DMA engine goes to fetch them below
|
|
*/
|
|
SSYNC();
|
|
|
|
/* enable this packet's dma */
|
|
current_tx_ptr->desc_a.config |= DMAEN;
|
|
|
|
/* tx dma is running, just return */
|
|
if (bfin_read_DMA2_IRQ_STATUS() & DMA_RUN)
|
|
goto out;
|
|
|
|
/* tx dma is not running */
|
|
bfin_write_DMA2_NEXT_DESC_PTR(&(current_tx_ptr->desc_a));
|
|
/* dma enabled, read from memory, size is 6 */
|
|
bfin_write_DMA2_CONFIG(current_tx_ptr->desc_a.config);
|
|
/* Turn on the EMAC tx */
|
|
bfin_write_EMAC_OPMODE(bfin_read_EMAC_OPMODE() | TE);
|
|
|
|
out:
|
|
adjust_tx_list();
|
|
current_tx_ptr = current_tx_ptr->next;
|
|
dev->trans_start = jiffies;
|
|
dev->stats.tx_packets++;
|
|
dev->stats.tx_bytes += (skb->len);
|
|
return NETDEV_TX_OK;
|
|
}
|
|
|
|
static void bfin_mac_rx(struct net_device *dev)
|
|
{
|
|
struct sk_buff *skb, *new_skb;
|
|
unsigned short len;
|
|
|
|
/* allocate a new skb for next time receive */
|
|
skb = current_rx_ptr->skb;
|
|
new_skb = dev_alloc_skb(PKT_BUF_SZ + NET_IP_ALIGN);
|
|
if (!new_skb) {
|
|
printk(KERN_NOTICE DRV_NAME
|
|
": rx: low on mem - packet dropped\n");
|
|
dev->stats.rx_dropped++;
|
|
goto out;
|
|
}
|
|
/* reserve 2 bytes for RXDWA padding */
|
|
skb_reserve(new_skb, NET_IP_ALIGN);
|
|
current_rx_ptr->skb = new_skb;
|
|
current_rx_ptr->desc_a.start_addr = (unsigned long)new_skb->data - 2;
|
|
|
|
/* Invidate the data cache of skb->data range when it is write back
|
|
* cache. It will prevent overwritting the new data from DMA
|
|
*/
|
|
blackfin_dcache_invalidate_range((unsigned long)new_skb->head,
|
|
(unsigned long)new_skb->end);
|
|
|
|
len = (unsigned short)((current_rx_ptr->status.status_word) & RX_FRLEN);
|
|
skb_put(skb, len);
|
|
blackfin_dcache_invalidate_range((unsigned long)skb->head,
|
|
(unsigned long)skb->tail);
|
|
|
|
skb->protocol = eth_type_trans(skb, dev);
|
|
#if defined(BFIN_MAC_CSUM_OFFLOAD)
|
|
skb->csum = current_rx_ptr->status.ip_payload_csum;
|
|
skb->ip_summed = CHECKSUM_COMPLETE;
|
|
#endif
|
|
|
|
netif_rx(skb);
|
|
dev->stats.rx_packets++;
|
|
dev->stats.rx_bytes += len;
|
|
current_rx_ptr->status.status_word = 0x00000000;
|
|
current_rx_ptr = current_rx_ptr->next;
|
|
|
|
out:
|
|
return;
|
|
}
|
|
|
|
/* interrupt routine to handle rx and error signal */
|
|
static irqreturn_t bfin_mac_interrupt(int irq, void *dev_id)
|
|
{
|
|
struct net_device *dev = dev_id;
|
|
int number = 0;
|
|
|
|
get_one_packet:
|
|
if (current_rx_ptr->status.status_word == 0) {
|
|
/* no more new packet received */
|
|
if (number == 0) {
|
|
if (current_rx_ptr->next->status.status_word != 0) {
|
|
current_rx_ptr = current_rx_ptr->next;
|
|
goto real_rx;
|
|
}
|
|
}
|
|
bfin_write_DMA1_IRQ_STATUS(bfin_read_DMA1_IRQ_STATUS() |
|
|
DMA_DONE | DMA_ERR);
|
|
return IRQ_HANDLED;
|
|
}
|
|
|
|
real_rx:
|
|
bfin_mac_rx(dev);
|
|
number++;
|
|
goto get_one_packet;
|
|
}
|
|
|
|
#ifdef CONFIG_NET_POLL_CONTROLLER
|
|
static void bfin_mac_poll(struct net_device *dev)
|
|
{
|
|
disable_irq(IRQ_MAC_RX);
|
|
bfin_mac_interrupt(IRQ_MAC_RX, dev);
|
|
enable_irq(IRQ_MAC_RX);
|
|
}
|
|
#endif /* CONFIG_NET_POLL_CONTROLLER */
|
|
|
|
static void bfin_mac_disable(void)
|
|
{
|
|
unsigned int opmode;
|
|
|
|
opmode = bfin_read_EMAC_OPMODE();
|
|
opmode &= (~RE);
|
|
opmode &= (~TE);
|
|
/* Turn off the EMAC */
|
|
bfin_write_EMAC_OPMODE(opmode);
|
|
}
|
|
|
|
/*
|
|
* Enable Interrupts, Receive, and Transmit
|
|
*/
|
|
static void bfin_mac_enable(void)
|
|
{
|
|
u32 opmode;
|
|
|
|
pr_debug("%s: %s\n", DRV_NAME, __func__);
|
|
|
|
/* Set RX DMA */
|
|
bfin_write_DMA1_NEXT_DESC_PTR(&(rx_list_head->desc_a));
|
|
bfin_write_DMA1_CONFIG(rx_list_head->desc_a.config);
|
|
|
|
/* Wait MII done */
|
|
bfin_mdio_poll();
|
|
|
|
/* We enable only RX here */
|
|
/* ASTP : Enable Automatic Pad Stripping
|
|
PR : Promiscuous Mode for test
|
|
PSF : Receive frames with total length less than 64 bytes.
|
|
FDMODE : Full Duplex Mode
|
|
LB : Internal Loopback for test
|
|
RE : Receiver Enable */
|
|
opmode = bfin_read_EMAC_OPMODE();
|
|
if (opmode & FDMODE)
|
|
opmode |= PSF;
|
|
else
|
|
opmode |= DRO | DC | PSF;
|
|
opmode |= RE;
|
|
|
|
#if defined(CONFIG_BFIN_MAC_RMII)
|
|
opmode |= RMII; /* For Now only 100MBit are supported */
|
|
#if (defined(CONFIG_BF537) || defined(CONFIG_BF536)) && CONFIG_BF_REV_0_2
|
|
opmode |= TE;
|
|
#endif
|
|
#endif
|
|
/* Turn on the EMAC rx */
|
|
bfin_write_EMAC_OPMODE(opmode);
|
|
}
|
|
|
|
/* Our watchdog timed out. Called by the networking layer */
|
|
static void bfin_mac_timeout(struct net_device *dev)
|
|
{
|
|
pr_debug("%s: %s\n", dev->name, __func__);
|
|
|
|
bfin_mac_disable();
|
|
|
|
/* reset tx queue */
|
|
tx_list_tail = tx_list_head->next;
|
|
|
|
bfin_mac_enable();
|
|
|
|
/* We can accept TX packets again */
|
|
dev->trans_start = jiffies;
|
|
netif_wake_queue(dev);
|
|
}
|
|
|
|
static void bfin_mac_multicast_hash(struct net_device *dev)
|
|
{
|
|
u32 emac_hashhi, emac_hashlo;
|
|
struct dev_mc_list *dmi = dev->mc_list;
|
|
char *addrs;
|
|
int i;
|
|
u32 crc;
|
|
|
|
emac_hashhi = emac_hashlo = 0;
|
|
|
|
for (i = 0; i < dev->mc_count; i++) {
|
|
addrs = dmi->dmi_addr;
|
|
dmi = dmi->next;
|
|
|
|
/* skip non-multicast addresses */
|
|
if (!(*addrs & 1))
|
|
continue;
|
|
|
|
crc = ether_crc(ETH_ALEN, addrs);
|
|
crc >>= 26;
|
|
|
|
if (crc & 0x20)
|
|
emac_hashhi |= 1 << (crc & 0x1f);
|
|
else
|
|
emac_hashlo |= 1 << (crc & 0x1f);
|
|
}
|
|
|
|
bfin_write_EMAC_HASHHI(emac_hashhi);
|
|
bfin_write_EMAC_HASHLO(emac_hashlo);
|
|
|
|
return;
|
|
}
|
|
|
|
/*
|
|
* This routine will, depending on the values passed to it,
|
|
* either make it accept multicast packets, go into
|
|
* promiscuous mode (for TCPDUMP and cousins) or accept
|
|
* a select set of multicast packets
|
|
*/
|
|
static void bfin_mac_set_multicast_list(struct net_device *dev)
|
|
{
|
|
u32 sysctl;
|
|
|
|
if (dev->flags & IFF_PROMISC) {
|
|
printk(KERN_INFO "%s: set to promisc mode\n", dev->name);
|
|
sysctl = bfin_read_EMAC_OPMODE();
|
|
sysctl |= RAF;
|
|
bfin_write_EMAC_OPMODE(sysctl);
|
|
} else if (dev->flags & IFF_ALLMULTI) {
|
|
/* accept all multicast */
|
|
sysctl = bfin_read_EMAC_OPMODE();
|
|
sysctl |= PAM;
|
|
bfin_write_EMAC_OPMODE(sysctl);
|
|
} else if (dev->mc_count) {
|
|
/* set up multicast hash table */
|
|
sysctl = bfin_read_EMAC_OPMODE();
|
|
sysctl |= HM;
|
|
bfin_write_EMAC_OPMODE(sysctl);
|
|
bfin_mac_multicast_hash(dev);
|
|
} else {
|
|
/* clear promisc or multicast mode */
|
|
sysctl = bfin_read_EMAC_OPMODE();
|
|
sysctl &= ~(RAF | PAM);
|
|
bfin_write_EMAC_OPMODE(sysctl);
|
|
}
|
|
}
|
|
|
|
/*
|
|
* this puts the device in an inactive state
|
|
*/
|
|
static void bfin_mac_shutdown(struct net_device *dev)
|
|
{
|
|
/* Turn off the EMAC */
|
|
bfin_write_EMAC_OPMODE(0x00000000);
|
|
/* Turn off the EMAC RX DMA */
|
|
bfin_write_DMA1_CONFIG(0x0000);
|
|
bfin_write_DMA2_CONFIG(0x0000);
|
|
}
|
|
|
|
/*
|
|
* Open and Initialize the interface
|
|
*
|
|
* Set up everything, reset the card, etc..
|
|
*/
|
|
static int bfin_mac_open(struct net_device *dev)
|
|
{
|
|
struct bfin_mac_local *lp = netdev_priv(dev);
|
|
int retval;
|
|
pr_debug("%s: %s\n", dev->name, __func__);
|
|
|
|
/*
|
|
* Check that the address is valid. If its not, refuse
|
|
* to bring the device up. The user must specify an
|
|
* address using ifconfig eth0 hw ether xx:xx:xx:xx:xx:xx
|
|
*/
|
|
if (!is_valid_ether_addr(dev->dev_addr)) {
|
|
printk(KERN_WARNING DRV_NAME ": no valid ethernet hw addr\n");
|
|
return -EINVAL;
|
|
}
|
|
|
|
/* initial rx and tx list */
|
|
retval = desc_list_init();
|
|
|
|
if (retval)
|
|
return retval;
|
|
|
|
phy_start(lp->phydev);
|
|
phy_write(lp->phydev, MII_BMCR, BMCR_RESET);
|
|
setup_system_regs(dev);
|
|
setup_mac_addr(dev->dev_addr);
|
|
bfin_mac_disable();
|
|
bfin_mac_enable();
|
|
pr_debug("hardware init finished\n");
|
|
netif_start_queue(dev);
|
|
netif_carrier_on(dev);
|
|
|
|
return 0;
|
|
}
|
|
|
|
/*
|
|
* this makes the board clean up everything that it can
|
|
* and not talk to the outside world. Caused by
|
|
* an 'ifconfig ethX down'
|
|
*/
|
|
static int bfin_mac_close(struct net_device *dev)
|
|
{
|
|
struct bfin_mac_local *lp = netdev_priv(dev);
|
|
pr_debug("%s: %s\n", dev->name, __func__);
|
|
|
|
netif_stop_queue(dev);
|
|
netif_carrier_off(dev);
|
|
|
|
phy_stop(lp->phydev);
|
|
phy_write(lp->phydev, MII_BMCR, BMCR_PDOWN);
|
|
|
|
/* clear everything */
|
|
bfin_mac_shutdown(dev);
|
|
|
|
/* free the rx/tx buffers */
|
|
desc_list_free();
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct net_device_ops bfin_mac_netdev_ops = {
|
|
.ndo_open = bfin_mac_open,
|
|
.ndo_stop = bfin_mac_close,
|
|
.ndo_start_xmit = bfin_mac_hard_start_xmit,
|
|
.ndo_set_mac_address = bfin_mac_set_mac_address,
|
|
.ndo_tx_timeout = bfin_mac_timeout,
|
|
.ndo_set_multicast_list = bfin_mac_set_multicast_list,
|
|
.ndo_validate_addr = eth_validate_addr,
|
|
.ndo_change_mtu = eth_change_mtu,
|
|
#ifdef CONFIG_NET_POLL_CONTROLLER
|
|
.ndo_poll_controller = bfin_mac_poll,
|
|
#endif
|
|
};
|
|
|
|
static int __devinit bfin_mac_probe(struct platform_device *pdev)
|
|
{
|
|
struct net_device *ndev;
|
|
struct bfin_mac_local *lp;
|
|
struct platform_device *pd;
|
|
int rc;
|
|
|
|
ndev = alloc_etherdev(sizeof(struct bfin_mac_local));
|
|
if (!ndev) {
|
|
dev_err(&pdev->dev, "Cannot allocate net device!\n");
|
|
return -ENOMEM;
|
|
}
|
|
|
|
SET_NETDEV_DEV(ndev, &pdev->dev);
|
|
platform_set_drvdata(pdev, ndev);
|
|
lp = netdev_priv(ndev);
|
|
|
|
/* Grab the MAC address in the MAC */
|
|
*(__le32 *) (&(ndev->dev_addr[0])) = cpu_to_le32(bfin_read_EMAC_ADDRLO());
|
|
*(__le16 *) (&(ndev->dev_addr[4])) = cpu_to_le16((u16) bfin_read_EMAC_ADDRHI());
|
|
|
|
/* probe mac */
|
|
/*todo: how to proble? which is revision_register */
|
|
bfin_write_EMAC_ADDRLO(0x12345678);
|
|
if (bfin_read_EMAC_ADDRLO() != 0x12345678) {
|
|
dev_err(&pdev->dev, "Cannot detect Blackfin on-chip ethernet MAC controller!\n");
|
|
rc = -ENODEV;
|
|
goto out_err_probe_mac;
|
|
}
|
|
|
|
|
|
/*
|
|
* Is it valid? (Did bootloader initialize it?)
|
|
* Grab the MAC from the board somehow
|
|
* this is done in the arch/blackfin/mach-bfxxx/boards/eth_mac.c
|
|
*/
|
|
if (!is_valid_ether_addr(ndev->dev_addr))
|
|
bfin_get_ether_addr(ndev->dev_addr);
|
|
|
|
/* If still not valid, get a random one */
|
|
if (!is_valid_ether_addr(ndev->dev_addr))
|
|
random_ether_addr(ndev->dev_addr);
|
|
|
|
setup_mac_addr(ndev->dev_addr);
|
|
|
|
if (!pdev->dev.platform_data) {
|
|
dev_err(&pdev->dev, "Cannot get platform device bfin_mii_bus!\n");
|
|
rc = -ENODEV;
|
|
goto out_err_probe_mac;
|
|
}
|
|
pd = pdev->dev.platform_data;
|
|
lp->mii_bus = platform_get_drvdata(pd);
|
|
lp->mii_bus->priv = ndev;
|
|
|
|
rc = mii_probe(ndev);
|
|
if (rc) {
|
|
dev_err(&pdev->dev, "MII Probe failed!\n");
|
|
goto out_err_mii_probe;
|
|
}
|
|
|
|
/* Fill in the fields of the device structure with ethernet values. */
|
|
ether_setup(ndev);
|
|
|
|
ndev->netdev_ops = &bfin_mac_netdev_ops;
|
|
ndev->ethtool_ops = &bfin_mac_ethtool_ops;
|
|
|
|
spin_lock_init(&lp->lock);
|
|
|
|
/* now, enable interrupts */
|
|
/* register irq handler */
|
|
rc = request_irq(IRQ_MAC_RX, bfin_mac_interrupt,
|
|
IRQF_DISABLED, "EMAC_RX", ndev);
|
|
if (rc) {
|
|
dev_err(&pdev->dev, "Cannot request Blackfin MAC RX IRQ!\n");
|
|
rc = -EBUSY;
|
|
goto out_err_request_irq;
|
|
}
|
|
|
|
rc = register_netdev(ndev);
|
|
if (rc) {
|
|
dev_err(&pdev->dev, "Cannot register net device!\n");
|
|
goto out_err_reg_ndev;
|
|
}
|
|
|
|
/* now, print out the card info, in a short format.. */
|
|
dev_info(&pdev->dev, "%s, Version %s\n", DRV_DESC, DRV_VERSION);
|
|
|
|
return 0;
|
|
|
|
out_err_reg_ndev:
|
|
free_irq(IRQ_MAC_RX, ndev);
|
|
out_err_request_irq:
|
|
out_err_mii_probe:
|
|
mdiobus_unregister(lp->mii_bus);
|
|
mdiobus_free(lp->mii_bus);
|
|
peripheral_free_list(pin_req);
|
|
out_err_probe_mac:
|
|
platform_set_drvdata(pdev, NULL);
|
|
free_netdev(ndev);
|
|
|
|
return rc;
|
|
}
|
|
|
|
static int __devexit bfin_mac_remove(struct platform_device *pdev)
|
|
{
|
|
struct net_device *ndev = platform_get_drvdata(pdev);
|
|
struct bfin_mac_local *lp = netdev_priv(ndev);
|
|
|
|
platform_set_drvdata(pdev, NULL);
|
|
|
|
lp->mii_bus->priv = NULL;
|
|
|
|
unregister_netdev(ndev);
|
|
|
|
free_irq(IRQ_MAC_RX, ndev);
|
|
|
|
free_netdev(ndev);
|
|
|
|
peripheral_free_list(pin_req);
|
|
|
|
return 0;
|
|
}
|
|
|
|
#ifdef CONFIG_PM
|
|
static int bfin_mac_suspend(struct platform_device *pdev, pm_message_t mesg)
|
|
{
|
|
struct net_device *net_dev = platform_get_drvdata(pdev);
|
|
|
|
if (netif_running(net_dev))
|
|
bfin_mac_close(net_dev);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int bfin_mac_resume(struct platform_device *pdev)
|
|
{
|
|
struct net_device *net_dev = platform_get_drvdata(pdev);
|
|
|
|
if (netif_running(net_dev))
|
|
bfin_mac_open(net_dev);
|
|
|
|
return 0;
|
|
}
|
|
#else
|
|
#define bfin_mac_suspend NULL
|
|
#define bfin_mac_resume NULL
|
|
#endif /* CONFIG_PM */
|
|
|
|
static int __devinit bfin_mii_bus_probe(struct platform_device *pdev)
|
|
{
|
|
struct mii_bus *miibus;
|
|
int rc, i;
|
|
|
|
/*
|
|
* We are setting up a network card,
|
|
* so set the GPIO pins to Ethernet mode
|
|
*/
|
|
rc = peripheral_request_list(pin_req, DRV_NAME);
|
|
if (rc) {
|
|
dev_err(&pdev->dev, "Requesting peripherals failed!\n");
|
|
return rc;
|
|
}
|
|
|
|
rc = -ENOMEM;
|
|
miibus = mdiobus_alloc();
|
|
if (miibus == NULL)
|
|
goto out_err_alloc;
|
|
miibus->read = bfin_mdiobus_read;
|
|
miibus->write = bfin_mdiobus_write;
|
|
miibus->reset = bfin_mdiobus_reset;
|
|
|
|
miibus->parent = &pdev->dev;
|
|
miibus->name = "bfin_mii_bus";
|
|
snprintf(miibus->id, MII_BUS_ID_SIZE, "0");
|
|
miibus->irq = kmalloc(sizeof(int)*PHY_MAX_ADDR, GFP_KERNEL);
|
|
if (miibus->irq == NULL)
|
|
goto out_err_alloc;
|
|
for (i = 0; i < PHY_MAX_ADDR; ++i)
|
|
miibus->irq[i] = PHY_POLL;
|
|
|
|
rc = mdiobus_register(miibus);
|
|
if (rc) {
|
|
dev_err(&pdev->dev, "Cannot register MDIO bus!\n");
|
|
goto out_err_mdiobus_register;
|
|
}
|
|
|
|
platform_set_drvdata(pdev, miibus);
|
|
return 0;
|
|
|
|
out_err_mdiobus_register:
|
|
mdiobus_free(miibus);
|
|
out_err_alloc:
|
|
peripheral_free_list(pin_req);
|
|
|
|
return rc;
|
|
}
|
|
|
|
static int __devexit bfin_mii_bus_remove(struct platform_device *pdev)
|
|
{
|
|
struct mii_bus *miibus = platform_get_drvdata(pdev);
|
|
platform_set_drvdata(pdev, NULL);
|
|
mdiobus_unregister(miibus);
|
|
mdiobus_free(miibus);
|
|
peripheral_free_list(pin_req);
|
|
return 0;
|
|
}
|
|
|
|
static struct platform_driver bfin_mii_bus_driver = {
|
|
.probe = bfin_mii_bus_probe,
|
|
.remove = __devexit_p(bfin_mii_bus_remove),
|
|
.driver = {
|
|
.name = "bfin_mii_bus",
|
|
.owner = THIS_MODULE,
|
|
},
|
|
};
|
|
|
|
static struct platform_driver bfin_mac_driver = {
|
|
.probe = bfin_mac_probe,
|
|
.remove = __devexit_p(bfin_mac_remove),
|
|
.resume = bfin_mac_resume,
|
|
.suspend = bfin_mac_suspend,
|
|
.driver = {
|
|
.name = DRV_NAME,
|
|
.owner = THIS_MODULE,
|
|
},
|
|
};
|
|
|
|
static int __init bfin_mac_init(void)
|
|
{
|
|
int ret;
|
|
ret = platform_driver_register(&bfin_mii_bus_driver);
|
|
if (!ret)
|
|
return platform_driver_register(&bfin_mac_driver);
|
|
return -ENODEV;
|
|
}
|
|
|
|
module_init(bfin_mac_init);
|
|
|
|
static void __exit bfin_mac_cleanup(void)
|
|
{
|
|
platform_driver_unregister(&bfin_mac_driver);
|
|
platform_driver_unregister(&bfin_mii_bus_driver);
|
|
}
|
|
|
|
module_exit(bfin_mac_cleanup);
|
|
|