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a98b38b83d
During GPIO testing on PiMX1 board there has been revealed problem with some pins input functions. The GIUS bit has to be set for inputs to work reliably too. It is surprising that input worked on some inputs with incorrect setup before. DR is not mandatory, but it ensures stable constant level on internal traces. Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz> Acked-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
385 lines
8.5 KiB
C
385 lines
8.5 KiB
C
/*
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* arch/arm/mach-imx/generic.c
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*
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* author: Sascha Hauer
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* Created: april 20th, 2004
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* Copyright: Synertronixx GmbH
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*
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* Common code for i.MX machines
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*
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*/
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#include <linux/platform_device.h>
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/string.h>
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#include <asm/errno.h>
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#include <asm/arch/imxfb.h>
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#include <asm/hardware.h>
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#include <asm/arch/imx-regs.h>
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#include <asm/mach/map.h>
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#include <asm/arch/mmc.h>
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#include <asm/arch/gpio.h>
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unsigned long imx_gpio_alloc_map[(GPIO_PORT_MAX + 1) * 32 / BITS_PER_LONG];
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void imx_gpio_mode(int gpio_mode)
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{
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unsigned int pin = gpio_mode & GPIO_PIN_MASK;
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unsigned int port = (gpio_mode & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT;
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unsigned int ocr = (gpio_mode & GPIO_OCR_MASK) >> GPIO_OCR_SHIFT;
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unsigned int tmp;
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/* Pullup enable */
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if(gpio_mode & GPIO_PUEN)
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PUEN(port) |= (1<<pin);
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else
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PUEN(port) &= ~(1<<pin);
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/* Data direction */
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if(gpio_mode & GPIO_OUT)
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DDIR(port) |= 1<<pin;
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else
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DDIR(port) &= ~(1<<pin);
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/* Primary / alternate function */
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if(gpio_mode & GPIO_AF)
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GPR(port) |= (1<<pin);
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else
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GPR(port) &= ~(1<<pin);
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/* use as gpio? */
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if(gpio_mode & GPIO_GIUS)
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GIUS(port) |= (1<<pin);
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else
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GIUS(port) &= ~(1<<pin);
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/* Output / input configuration */
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/* FIXME: I'm not very sure about OCR and ICONF, someone
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* should have a look over it
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*/
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if(pin<16) {
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tmp = OCR1(port);
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tmp &= ~( 3<<(pin*2));
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tmp |= (ocr << (pin*2));
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OCR1(port) = tmp;
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ICONFA1(port) &= ~( 3<<(pin*2));
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ICONFA1(port) |= ((gpio_mode >> GPIO_AOUT_SHIFT) & 3) << (pin * 2);
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ICONFB1(port) &= ~( 3<<(pin*2));
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ICONFB1(port) |= ((gpio_mode >> GPIO_BOUT_SHIFT) & 3) << (pin * 2);
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} else {
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tmp = OCR2(port);
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tmp &= ~( 3<<((pin-16)*2));
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tmp |= (ocr << ((pin-16)*2));
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OCR2(port) = tmp;
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ICONFA2(port) &= ~( 3<<((pin-16)*2));
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ICONFA2(port) |= ((gpio_mode >> GPIO_AOUT_SHIFT) & 3) << ((pin-16) * 2);
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ICONFB2(port) &= ~( 3<<((pin-16)*2));
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ICONFB2(port) |= ((gpio_mode >> GPIO_BOUT_SHIFT) & 3) << ((pin-16) * 2);
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}
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}
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EXPORT_SYMBOL(imx_gpio_mode);
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int imx_gpio_request(unsigned gpio, const char *label)
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{
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if(gpio >= (GPIO_PORT_MAX + 1) * 32) {
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printk(KERN_ERR "imx_gpio: Attempt to request nonexistent GPIO %d for \"%s\"\n",
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gpio, label ? label : "?");
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return -EINVAL;
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}
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if(test_and_set_bit(gpio, imx_gpio_alloc_map)) {
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printk(KERN_ERR "imx_gpio: GPIO %d already used. Allocation for \"%s\" failed\n",
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gpio, label ? label : "?");
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return -EBUSY;
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}
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return 0;
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}
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EXPORT_SYMBOL(imx_gpio_request);
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void imx_gpio_free(unsigned gpio)
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{
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if(gpio >= (GPIO_PORT_MAX + 1) * 32)
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return;
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clear_bit(gpio, imx_gpio_alloc_map);
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}
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EXPORT_SYMBOL(imx_gpio_free);
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int imx_gpio_direction_input(unsigned gpio)
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{
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imx_gpio_mode(gpio | GPIO_IN | GPIO_GIUS | GPIO_DR);
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return 0;
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}
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EXPORT_SYMBOL(imx_gpio_direction_input);
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int imx_gpio_direction_output(unsigned gpio, int value)
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{
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imx_gpio_set_value(gpio, value);
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imx_gpio_mode(gpio | GPIO_OUT | GPIO_GIUS | GPIO_DR);
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return 0;
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}
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EXPORT_SYMBOL(imx_gpio_direction_output);
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int imx_gpio_setup_multiple_pins(const int *pin_list, unsigned count,
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int alloc_mode, const char *label)
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{
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const int *p = pin_list;
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int i;
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unsigned gpio;
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unsigned mode;
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for (i = 0; i < count; i++) {
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gpio = *p & (GPIO_PIN_MASK | GPIO_PORT_MASK);
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mode = *p & ~(GPIO_PIN_MASK | GPIO_PORT_MASK);
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if (gpio >= (GPIO_PORT_MAX + 1) * 32)
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goto setup_error;
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if (alloc_mode & IMX_GPIO_ALLOC_MODE_RELEASE)
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imx_gpio_free(gpio);
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else if (!(alloc_mode & IMX_GPIO_ALLOC_MODE_NO_ALLOC))
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if (imx_gpio_request(gpio, label))
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if (!(alloc_mode & IMX_GPIO_ALLOC_MODE_TRY_ALLOC))
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goto setup_error;
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if (!(alloc_mode & (IMX_GPIO_ALLOC_MODE_ALLOC_ONLY |
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IMX_GPIO_ALLOC_MODE_RELEASE)))
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imx_gpio_mode(gpio | mode);
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p++;
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}
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return 0;
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setup_error:
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if(alloc_mode & (IMX_GPIO_ALLOC_MODE_NO_ALLOC |
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IMX_GPIO_ALLOC_MODE_TRY_ALLOC))
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return -EINVAL;
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while (p != pin_list) {
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p--;
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gpio = *p & (GPIO_PIN_MASK | GPIO_PORT_MASK);
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imx_gpio_free(gpio);
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}
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return -EINVAL;
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}
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EXPORT_SYMBOL(imx_gpio_setup_multiple_pins);
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void __imx_gpio_set_value(unsigned gpio, int value)
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{
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imx_gpio_set_value_inline(gpio, value);
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}
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EXPORT_SYMBOL(__imx_gpio_set_value);
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int imx_gpio_to_irq(unsigned gpio)
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{
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return IRQ_GPIOA(0) + gpio;
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}
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EXPORT_SYMBOL(imx_gpio_to_irq);
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int imx_irq_to_gpio(unsigned irq)
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{
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if (irq < IRQ_GPIOA(0))
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return -EINVAL;
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return irq - IRQ_GPIOA(0);
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}
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EXPORT_SYMBOL(imx_irq_to_gpio);
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/*
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* get the system pll clock in Hz
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*
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* mfi + mfn / (mfd +1)
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* f = 2 * f_ref * --------------------
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* pd + 1
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*/
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static unsigned int imx_decode_pll(unsigned int pll, u32 f_ref)
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{
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unsigned long long ll;
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unsigned long quot;
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u32 mfi = (pll >> 10) & 0xf;
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u32 mfn = pll & 0x3ff;
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u32 mfd = (pll >> 16) & 0x3ff;
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u32 pd = (pll >> 26) & 0xf;
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mfi = mfi <= 5 ? 5 : mfi;
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ll = 2 * (unsigned long long)f_ref * ( (mfi<<16) + (mfn<<16) / (mfd+1) );
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quot = (pd+1) * (1<<16);
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ll += quot / 2;
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do_div(ll, quot);
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return (unsigned int) ll;
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}
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unsigned int imx_get_system_clk(void)
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{
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u32 f_ref = (CSCR & CSCR_SYSTEM_SEL) ? 16000000 : (CLK32 * 512);
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return imx_decode_pll(SPCTL0, f_ref);
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}
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EXPORT_SYMBOL(imx_get_system_clk);
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unsigned int imx_get_mcu_clk(void)
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{
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return imx_decode_pll(MPCTL0, CLK32 * 512);
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}
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EXPORT_SYMBOL(imx_get_mcu_clk);
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/*
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* get peripheral clock 1 ( UART[12], Timer[12], PWM )
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*/
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unsigned int imx_get_perclk1(void)
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{
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return imx_get_system_clk() / (((PCDR) & 0xf)+1);
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}
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EXPORT_SYMBOL(imx_get_perclk1);
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/*
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* get peripheral clock 2 ( LCD, SD, SPI[12] )
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*/
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unsigned int imx_get_perclk2(void)
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{
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return imx_get_system_clk() / (((PCDR>>4) & 0xf)+1);
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}
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EXPORT_SYMBOL(imx_get_perclk2);
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/*
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* get peripheral clock 3 ( SSI )
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*/
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unsigned int imx_get_perclk3(void)
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{
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return imx_get_system_clk() / (((PCDR>>16) & 0x7f)+1);
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}
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EXPORT_SYMBOL(imx_get_perclk3);
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/*
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* get hclk ( SDRAM, CSI, Memory Stick, I2C, DMA )
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*/
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unsigned int imx_get_hclk(void)
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{
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return imx_get_system_clk() / (((CSCR>>10) & 0xf)+1);
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}
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EXPORT_SYMBOL(imx_get_hclk);
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static struct resource imx_mmc_resources[] = {
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[0] = {
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.start = 0x00214000,
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.end = 0x002140FF,
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.flags = IORESOURCE_MEM,
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},
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[1] = {
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.start = (SDHC_INT),
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.end = (SDHC_INT),
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.flags = IORESOURCE_IRQ,
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},
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};
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static u64 imxmmmc_dmamask = 0xffffffffUL;
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static struct platform_device imx_mmc_device = {
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.name = "imx-mmc",
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.id = 0,
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.dev = {
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.dma_mask = &imxmmmc_dmamask,
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.coherent_dma_mask = 0xffffffff,
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},
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.num_resources = ARRAY_SIZE(imx_mmc_resources),
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.resource = imx_mmc_resources,
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};
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void __init imx_set_mmc_info(struct imxmmc_platform_data *info)
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{
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imx_mmc_device.dev.platform_data = info;
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}
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static struct imxfb_mach_info imx_fb_info;
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void __init set_imx_fb_info(struct imxfb_mach_info *hard_imx_fb_info)
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{
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memcpy(&imx_fb_info,hard_imx_fb_info,sizeof(struct imxfb_mach_info));
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}
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EXPORT_SYMBOL(set_imx_fb_info);
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static struct resource imxfb_resources[] = {
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[0] = {
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.start = 0x00205000,
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.end = 0x002050FF,
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.flags = IORESOURCE_MEM,
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},
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[1] = {
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.start = LCDC_INT,
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.end = LCDC_INT,
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.flags = IORESOURCE_IRQ,
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},
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};
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static u64 fb_dma_mask = ~(u64)0;
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static struct platform_device imxfb_device = {
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.name = "imx-fb",
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.id = 0,
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.dev = {
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.platform_data = &imx_fb_info,
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.dma_mask = &fb_dma_mask,
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.coherent_dma_mask = 0xffffffff,
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},
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.num_resources = ARRAY_SIZE(imxfb_resources),
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.resource = imxfb_resources,
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};
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static struct platform_device *devices[] __initdata = {
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&imx_mmc_device,
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&imxfb_device,
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};
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static struct map_desc imx_io_desc[] __initdata = {
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{
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.virtual = IMX_IO_BASE,
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.pfn = __phys_to_pfn(IMX_IO_PHYS),
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.length = IMX_IO_SIZE,
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.type = MT_DEVICE
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}
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};
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void __init
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imx_map_io(void)
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{
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iotable_init(imx_io_desc, ARRAY_SIZE(imx_io_desc));
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}
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static int __init imx_init(void)
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{
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return platform_add_devices(devices, ARRAY_SIZE(devices));
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}
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subsys_initcall(imx_init);
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