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543876c928
If the PM support is available this is passed through the platform instead to be hard-coded in the core files. WoL on Magic Frame can be enabled by using the ethtool support. Signed-off-by: Giuseppe Cavallaro <peppe.cavallaro@st.com> Signed-off-by: David S. Miller <davem@davemloft.net>
204 lines
6.6 KiB
C
204 lines
6.6 KiB
C
/*******************************************************************************
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This is the driver for the MAC 10/100 on-chip Ethernet controller
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currently tested on all the ST boards based on STb7109 and stx7200 SoCs.
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DWC Ether MAC 10/100 Universal version 4.0 has been used for developing
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this code.
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This only implements the mac core functions for this chip.
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Copyright (C) 2007-2009 STMicroelectronics Ltd
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This program is free software; you can redistribute it and/or modify it
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under the terms and conditions of the GNU General Public License,
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version 2, as published by the Free Software Foundation.
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This program is distributed in the hope it will be useful, but WITHOUT
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ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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more details.
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You should have received a copy of the GNU General Public License along with
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this program; if not, write to the Free Software Foundation, Inc.,
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51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
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The full GNU General Public License is included in this distribution in
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the file called "COPYING".
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Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
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*******************************************************************************/
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#include <linux/crc32.h>
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#include "dwmac100.h"
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static void dwmac100_core_init(void __iomem *ioaddr)
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{
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u32 value = readl(ioaddr + MAC_CONTROL);
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writel((value | MAC_CORE_INIT), ioaddr + MAC_CONTROL);
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#ifdef STMMAC_VLAN_TAG_USED
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writel(ETH_P_8021Q, ioaddr + MAC_VLAN1);
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#endif
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}
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static int dwmac100_rx_coe_supported(void __iomem *ioaddr)
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{
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return 0;
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}
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static void dwmac100_dump_mac_regs(void __iomem *ioaddr)
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{
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pr_info("\t----------------------------------------------\n"
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"\t DWMAC 100 CSR (base addr = 0x%p)\n"
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"\t----------------------------------------------\n",
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ioaddr);
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pr_info("\tcontrol reg (offset 0x%x): 0x%08x\n", MAC_CONTROL,
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readl(ioaddr + MAC_CONTROL));
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pr_info("\taddr HI (offset 0x%x): 0x%08x\n ", MAC_ADDR_HIGH,
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readl(ioaddr + MAC_ADDR_HIGH));
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pr_info("\taddr LO (offset 0x%x): 0x%08x\n", MAC_ADDR_LOW,
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readl(ioaddr + MAC_ADDR_LOW));
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pr_info("\tmulticast hash HI (offset 0x%x): 0x%08x\n",
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MAC_HASH_HIGH, readl(ioaddr + MAC_HASH_HIGH));
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pr_info("\tmulticast hash LO (offset 0x%x): 0x%08x\n",
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MAC_HASH_LOW, readl(ioaddr + MAC_HASH_LOW));
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pr_info("\tflow control (offset 0x%x): 0x%08x\n",
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MAC_FLOW_CTRL, readl(ioaddr + MAC_FLOW_CTRL));
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pr_info("\tVLAN1 tag (offset 0x%x): 0x%08x\n", MAC_VLAN1,
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readl(ioaddr + MAC_VLAN1));
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pr_info("\tVLAN2 tag (offset 0x%x): 0x%08x\n", MAC_VLAN2,
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readl(ioaddr + MAC_VLAN2));
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pr_info("\n\tMAC management counter registers\n");
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pr_info("\t MMC crtl (offset 0x%x): 0x%08x\n",
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MMC_CONTROL, readl(ioaddr + MMC_CONTROL));
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pr_info("\t MMC High Interrupt (offset 0x%x): 0x%08x\n",
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MMC_HIGH_INTR, readl(ioaddr + MMC_HIGH_INTR));
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pr_info("\t MMC Low Interrupt (offset 0x%x): 0x%08x\n",
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MMC_LOW_INTR, readl(ioaddr + MMC_LOW_INTR));
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pr_info("\t MMC High Interrupt Mask (offset 0x%x): 0x%08x\n",
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MMC_HIGH_INTR_MASK, readl(ioaddr + MMC_HIGH_INTR_MASK));
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pr_info("\t MMC Low Interrupt Mask (offset 0x%x): 0x%08x\n",
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MMC_LOW_INTR_MASK, readl(ioaddr + MMC_LOW_INTR_MASK));
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}
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static void dwmac100_irq_status(void __iomem *ioaddr)
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{
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return;
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}
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static void dwmac100_set_umac_addr(void __iomem *ioaddr, unsigned char *addr,
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unsigned int reg_n)
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{
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stmmac_set_mac_addr(ioaddr, addr, MAC_ADDR_HIGH, MAC_ADDR_LOW);
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}
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static void dwmac100_get_umac_addr(void __iomem *ioaddr, unsigned char *addr,
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unsigned int reg_n)
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{
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stmmac_get_mac_addr(ioaddr, addr, MAC_ADDR_HIGH, MAC_ADDR_LOW);
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}
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static void dwmac100_set_filter(struct net_device *dev)
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{
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void __iomem *ioaddr = (void __iomem *) dev->base_addr;
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u32 value = readl(ioaddr + MAC_CONTROL);
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if (dev->flags & IFF_PROMISC) {
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value |= MAC_CONTROL_PR;
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value &= ~(MAC_CONTROL_PM | MAC_CONTROL_IF | MAC_CONTROL_HO |
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MAC_CONTROL_HP);
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} else if ((netdev_mc_count(dev) > HASH_TABLE_SIZE)
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|| (dev->flags & IFF_ALLMULTI)) {
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value |= MAC_CONTROL_PM;
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value &= ~(MAC_CONTROL_PR | MAC_CONTROL_IF | MAC_CONTROL_HO);
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writel(0xffffffff, ioaddr + MAC_HASH_HIGH);
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writel(0xffffffff, ioaddr + MAC_HASH_LOW);
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} else if (netdev_mc_empty(dev)) { /* no multicast */
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value &= ~(MAC_CONTROL_PM | MAC_CONTROL_PR | MAC_CONTROL_IF |
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MAC_CONTROL_HO | MAC_CONTROL_HP);
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} else {
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u32 mc_filter[2];
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struct netdev_hw_addr *ha;
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/* Perfect filter mode for physical address and Hash
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filter for multicast */
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value |= MAC_CONTROL_HP;
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value &= ~(MAC_CONTROL_PM | MAC_CONTROL_PR |
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MAC_CONTROL_IF | MAC_CONTROL_HO);
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memset(mc_filter, 0, sizeof(mc_filter));
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netdev_for_each_mc_addr(ha, dev) {
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/* The upper 6 bits of the calculated CRC are used to
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* index the contens of the hash table */
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int bit_nr =
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ether_crc(ETH_ALEN, ha->addr) >> 26;
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/* The most significant bit determines the register to
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* use (H/L) while the other 5 bits determine the bit
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* within the register. */
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mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
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}
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writel(mc_filter[0], ioaddr + MAC_HASH_LOW);
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writel(mc_filter[1], ioaddr + MAC_HASH_HIGH);
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}
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writel(value, ioaddr + MAC_CONTROL);
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CHIP_DBG(KERN_INFO "%s: CTRL reg: 0x%08x Hash regs: "
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"HI 0x%08x, LO 0x%08x\n",
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__func__, readl(ioaddr + MAC_CONTROL),
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readl(ioaddr + MAC_HASH_HIGH), readl(ioaddr + MAC_HASH_LOW));
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}
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static void dwmac100_flow_ctrl(void __iomem *ioaddr, unsigned int duplex,
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unsigned int fc, unsigned int pause_time)
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{
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unsigned int flow = MAC_FLOW_CTRL_ENABLE;
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if (duplex)
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flow |= (pause_time << MAC_FLOW_CTRL_PT_SHIFT);
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writel(flow, ioaddr + MAC_FLOW_CTRL);
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}
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/* No PMT module supported for this Ethernet Controller.
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* Tested on ST platforms only.
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*/
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static void dwmac100_pmt(void __iomem *ioaddr, unsigned long mode)
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{
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return;
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}
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struct stmmac_ops dwmac100_ops = {
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.core_init = dwmac100_core_init,
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.rx_coe = dwmac100_rx_coe_supported,
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.dump_regs = dwmac100_dump_mac_regs,
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.host_irq_status = dwmac100_irq_status,
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.set_filter = dwmac100_set_filter,
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.flow_ctrl = dwmac100_flow_ctrl,
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.pmt = dwmac100_pmt,
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.set_umac_addr = dwmac100_set_umac_addr,
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.get_umac_addr = dwmac100_get_umac_addr,
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};
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struct mac_device_info *dwmac100_setup(void __iomem *ioaddr)
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{
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struct mac_device_info *mac;
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mac = kzalloc(sizeof(const struct mac_device_info), GFP_KERNEL);
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if (!mac)
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return NULL;
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pr_info("\tDWMAC100\n");
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mac->mac = &dwmac100_ops;
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mac->dma = &dwmac100_dma_ops;
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mac->link.port = MAC_CONTROL_PS;
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mac->link.duplex = MAC_CONTROL_F;
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mac->link.speed = 0;
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mac->mii.addr = MAC_MII_ADDR;
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mac->mii.data = MAC_MII_DATA;
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return mac;
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}
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