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bed61935cc
Add the new SPI write and read functions. The SPI read function is used for creating initial registers dump and may be used for debugging purposes. SPI operations are cached, so there is a new function to manage the cache (shadow). I have to remove the shift from the CS4245_SPI_* constants, since when we are performing the reading, we need to shift by 8 instead of 16. Signed-off-by: Roman Volkov <v1ron@mail.ru> Signed-off-by: Clemens Ladisch <clemens@ladisch.de>
111 lines
2.9 KiB
C
111 lines
2.9 KiB
C
#define CS4245_CHIP_ID 0x01
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#define CS4245_POWER_CTRL 0x02
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#define CS4245_DAC_CTRL_1 0x03
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#define CS4245_ADC_CTRL 0x04
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#define CS4245_MCLK_FREQ 0x05
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#define CS4245_SIGNAL_SEL 0x06
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#define CS4245_PGA_B_CTRL 0x07
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#define CS4245_PGA_A_CTRL 0x08
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#define CS4245_ANALOG_IN 0x09
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#define CS4245_DAC_A_CTRL 0x0a
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#define CS4245_DAC_B_CTRL 0x0b
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#define CS4245_DAC_CTRL_2 0x0c
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#define CS4245_INT_STATUS 0x0d
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#define CS4245_INT_MASK 0x0e
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#define CS4245_INT_MODE_MSB 0x0f
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#define CS4245_INT_MODE_LSB 0x10
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/* Chip ID */
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#define CS4245_CHIP_PART_MASK 0xf0
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#define CS4245_CHIP_REV_MASK 0x0f
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/* Power Control */
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#define CS4245_FREEZE 0x80
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#define CS4245_PDN_MIC 0x08
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#define CS4245_PDN_ADC 0x04
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#define CS4245_PDN_DAC 0x02
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#define CS4245_PDN 0x01
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/* DAC Control */
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#define CS4245_DAC_FM_MASK 0xc0
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#define CS4245_DAC_FM_SINGLE 0x00
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#define CS4245_DAC_FM_DOUBLE 0x40
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#define CS4245_DAC_FM_QUAD 0x80
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#define CS4245_DAC_DIF_MASK 0x30
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#define CS4245_DAC_DIF_LJUST 0x00
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#define CS4245_DAC_DIF_I2S 0x10
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#define CS4245_DAC_DIF_RJUST_16 0x20
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#define CS4245_DAC_DIF_RJUST_24 0x30
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#define CS4245_RESERVED_1 0x08
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#define CS4245_MUTE_DAC 0x04
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#define CS4245_DEEMPH 0x02
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#define CS4245_DAC_MASTER 0x01
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/* ADC Control */
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#define CS4245_ADC_FM_MASK 0xc0
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#define CS4245_ADC_FM_SINGLE 0x00
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#define CS4245_ADC_FM_DOUBLE 0x40
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#define CS4245_ADC_FM_QUAD 0x80
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#define CS4245_ADC_DIF_MASK 0x10
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#define CS4245_ADC_DIF_LJUST 0x00
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#define CS4245_ADC_DIF_I2S 0x10
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#define CS4245_MUTE_ADC 0x04
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#define CS4245_HPF_FREEZE 0x02
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#define CS4245_ADC_MASTER 0x01
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/* MCLK Frequency */
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#define CS4245_MCLK1_MASK 0x70
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#define CS4245_MCLK1_SHIFT 4
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#define CS4245_MCLK2_MASK 0x07
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#define CS4245_MCLK2_SHIFT 0
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#define CS4245_MCLK_1 0
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#define CS4245_MCLK_1_5 1
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#define CS4245_MCLK_2 2
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#define CS4245_MCLK_3 3
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#define CS4245_MCLK_4 4
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/* Signal Selection */
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#define CS4245_A_OUT_SEL_MASK 0x60
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#define CS4245_A_OUT_SEL_HIZ 0x00
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#define CS4245_A_OUT_SEL_DAC 0x20
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#define CS4245_A_OUT_SEL_PGA 0x40
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#define CS4245_LOOP 0x02
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#define CS4245_ASYNCH 0x01
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/* Channel B/A PGA Control */
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#define CS4245_PGA_GAIN_MASK 0x3f
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/* ADC Input Control */
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#define CS4245_PGA_SOFT 0x10
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#define CS4245_PGA_ZERO 0x08
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#define CS4245_SEL_MASK 0x07
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#define CS4245_SEL_MIC 0x00
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#define CS4245_SEL_INPUT_1 0x01
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#define CS4245_SEL_INPUT_2 0x02
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#define CS4245_SEL_INPUT_3 0x03
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#define CS4245_SEL_INPUT_4 0x04
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#define CS4245_SEL_INPUT_5 0x05
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#define CS4245_SEL_INPUT_6 0x06
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/* DAC Channel A/B Volume Control */
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#define CS4245_VOL_MASK 0xff
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/* DAC Control 2 */
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#define CS4245_DAC_SOFT 0x80
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#define CS4245_DAC_ZERO 0x40
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#define CS4245_INVERT_DAC 0x20
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#define CS4245_INT_ACTIVE_HIGH 0x01
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/* Interrupt Status/Mask/Mode */
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#define CS4245_ADC_CLK_ERR 0x08
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#define CS4245_DAC_CLK_ERR 0x04
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#define CS4245_ADC_OVFL 0x02
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#define CS4245_ADC_UNDRFL 0x01
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#define CS4245_SPI_ADDRESS_S (0x9e << 16)
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#define CS4245_SPI_WRITE_S (0 << 16)
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#define CS4245_SPI_ADDRESS 0x9e
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#define CS4245_SPI_WRITE 0
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#define CS4245_SPI_READ 1
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