mirror of
https://github.com/edk2-porting/linux-next.git
synced 2024-12-23 20:53:53 +08:00
405f55712d
* Remove smp_lock.h from files which don't need it (including some headers!) * Add smp_lock.h to files which do need it * Make smp_lock.h include conditional in hardirq.h It's needed only for one kernel_locked() usage which is under CONFIG_PREEMPT This will make hardirq.h inclusion cheaper for every PREEMPT=n config (which includes allmodconfig/allyesconfig, BTW) Signed-off-by: Alexey Dobriyan <adobriyan@gmail.com> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
97 lines
2.2 KiB
C
97 lines
2.2 KiB
C
/*
|
|
* arch/sh/mm/tlb-sh3.c
|
|
*
|
|
* SH-3 specific TLB operations
|
|
*
|
|
* Copyright (C) 1999 Niibe Yutaka
|
|
* Copyright (C) 2002 Paul Mundt
|
|
*
|
|
* Released under the terms of the GNU GPL v2.0.
|
|
*/
|
|
#include <linux/signal.h>
|
|
#include <linux/sched.h>
|
|
#include <linux/kernel.h>
|
|
#include <linux/errno.h>
|
|
#include <linux/string.h>
|
|
#include <linux/types.h>
|
|
#include <linux/ptrace.h>
|
|
#include <linux/mman.h>
|
|
#include <linux/mm.h>
|
|
#include <linux/smp.h>
|
|
#include <linux/interrupt.h>
|
|
|
|
#include <asm/system.h>
|
|
#include <asm/io.h>
|
|
#include <asm/uaccess.h>
|
|
#include <asm/pgalloc.h>
|
|
#include <asm/mmu_context.h>
|
|
#include <asm/cacheflush.h>
|
|
|
|
void update_mmu_cache(struct vm_area_struct * vma,
|
|
unsigned long address, pte_t pte)
|
|
{
|
|
unsigned long flags;
|
|
unsigned long pteval;
|
|
unsigned long vpn;
|
|
|
|
/* Ptrace may call this routine. */
|
|
if (vma && current->active_mm != vma->vm_mm)
|
|
return;
|
|
|
|
#if defined(CONFIG_SH7705_CACHE_32KB)
|
|
{
|
|
struct page *page = pte_page(pte);
|
|
unsigned long pfn = pte_pfn(pte);
|
|
|
|
if (pfn_valid(pfn) && !test_bit(PG_mapped, &page->flags)) {
|
|
unsigned long phys = pte_val(pte) & PTE_PHYS_MASK;
|
|
|
|
__flush_wback_region((void *)P1SEGADDR(phys),
|
|
PAGE_SIZE);
|
|
__set_bit(PG_mapped, &page->flags);
|
|
}
|
|
}
|
|
#endif
|
|
|
|
local_irq_save(flags);
|
|
|
|
/* Set PTEH register */
|
|
vpn = (address & MMU_VPN_MASK) | get_asid();
|
|
ctrl_outl(vpn, MMU_PTEH);
|
|
|
|
pteval = pte_val(pte);
|
|
|
|
/* Set PTEL register */
|
|
pteval &= _PAGE_FLAGS_HARDWARE_MASK; /* drop software flags */
|
|
/* conveniently, we want all the software flags to be 0 anyway */
|
|
ctrl_outl(pteval, MMU_PTEL);
|
|
|
|
/* Load the TLB */
|
|
asm volatile("ldtlb": /* no output */ : /* no input */ : "memory");
|
|
local_irq_restore(flags);
|
|
}
|
|
|
|
void local_flush_tlb_one(unsigned long asid, unsigned long page)
|
|
{
|
|
unsigned long addr, data;
|
|
int i, ways = MMU_NTLB_WAYS;
|
|
|
|
/*
|
|
* NOTE: PTEH.ASID should be set to this MM
|
|
* _AND_ we need to write ASID to the array.
|
|
*
|
|
* It would be simple if we didn't need to set PTEH.ASID...
|
|
*/
|
|
addr = MMU_TLB_ADDRESS_ARRAY | (page & 0x1F000);
|
|
data = (page & 0xfffe0000) | asid; /* VALID bit is off */
|
|
|
|
if ((current_cpu_data.flags & CPU_HAS_MMU_PAGE_ASSOC)) {
|
|
addr |= MMU_PAGE_ASSOC_BIT;
|
|
ways = 1; /* we already know the way .. */
|
|
}
|
|
|
|
for (i = 0; i < ways; i++)
|
|
ctrl_outl(data, addr + (i << 8));
|
|
}
|
|
|