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c80dfd9bf5
Add CRG driver for Hi3516CV300 SoC. CRG(Clock and Reset Generator) module generates clock and reset signals used by other module blocks on SoC. Signed-off-by: Pan Wen <wenpan@hisilicon.com> Signed-off-by: Jiancheng Xue <xuejiancheng@hisilicon.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
331 lines
10 KiB
C
331 lines
10 KiB
C
/*
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* Hi3516CV300 Clock and Reset Generator Driver
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*
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* Copyright (c) 2016 HiSilicon Technologies Co., Ltd.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <dt-bindings/clock/hi3516cv300-clock.h>
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#include <linux/clk-provider.h>
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#include <linux/module.h>
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#include <linux/of_device.h>
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#include <linux/platform_device.h>
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#include "clk.h"
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#include "crg.h"
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#include "reset.h"
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/* hi3516CV300 core CRG */
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#define HI3516CV300_INNER_CLK_OFFSET 64
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#define HI3516CV300_FIXED_3M 65
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#define HI3516CV300_FIXED_6M 66
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#define HI3516CV300_FIXED_24M 67
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#define HI3516CV300_FIXED_49P5 68
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#define HI3516CV300_FIXED_50M 69
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#define HI3516CV300_FIXED_83P3M 70
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#define HI3516CV300_FIXED_99M 71
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#define HI3516CV300_FIXED_100M 72
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#define HI3516CV300_FIXED_148P5M 73
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#define HI3516CV300_FIXED_198M 74
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#define HI3516CV300_FIXED_297M 75
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#define HI3516CV300_UART_MUX 76
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#define HI3516CV300_FMC_MUX 77
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#define HI3516CV300_MMC0_MUX 78
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#define HI3516CV300_MMC1_MUX 79
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#define HI3516CV300_MMC2_MUX 80
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#define HI3516CV300_MMC3_MUX 81
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#define HI3516CV300_PWM_MUX 82
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#define HI3516CV300_CRG_NR_CLKS 128
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static const struct hisi_fixed_rate_clock hi3516cv300_fixed_rate_clks[] = {
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{ HI3516CV300_FIXED_3M, "3m", NULL, 0, 3000000, },
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{ HI3516CV300_FIXED_6M, "6m", NULL, 0, 6000000, },
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{ HI3516CV300_FIXED_24M, "24m", NULL, 0, 24000000, },
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{ HI3516CV300_FIXED_49P5, "49.5m", NULL, 0, 49500000, },
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{ HI3516CV300_FIXED_50M, "50m", NULL, 0, 50000000, },
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{ HI3516CV300_FIXED_83P3M, "83.3m", NULL, 0, 83300000, },
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{ HI3516CV300_FIXED_99M, "99m", NULL, 0, 99000000, },
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{ HI3516CV300_FIXED_100M, "100m", NULL, 0, 100000000, },
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{ HI3516CV300_FIXED_148P5M, "148.5m", NULL, 0, 148500000, },
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{ HI3516CV300_FIXED_198M, "198m", NULL, 0, 198000000, },
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{ HI3516CV300_FIXED_297M, "297m", NULL, 0, 297000000, },
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{ HI3516CV300_APB_CLK, "apb", NULL, 0, 50000000, },
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};
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static const char *const uart_mux_p[] = {"24m", "6m"};
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static const char *const fmc_mux_p[] = {
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"24m", "83.3m", "148.5m", "198m", "297m"
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};
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static const char *const mmc_mux_p[] = {"49.5m"};
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static const char *const mmc2_mux_p[] = {"99m", "49.5m"};
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static const char *const pwm_mux_p[] = {"3m", "50m", "24m", "24m"};
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static u32 uart_mux_table[] = {0, 1};
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static u32 fmc_mux_table[] = {0, 1, 2, 3, 4};
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static u32 mmc_mux_table[] = {0};
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static u32 mmc2_mux_table[] = {0, 2};
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static u32 pwm_mux_table[] = {0, 1, 2, 3};
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static const struct hisi_mux_clock hi3516cv300_mux_clks[] = {
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{ HI3516CV300_UART_MUX, "uart_mux", uart_mux_p, ARRAY_SIZE(uart_mux_p),
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CLK_SET_RATE_PARENT, 0xe4, 19, 1, 0, uart_mux_table, },
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{ HI3516CV300_FMC_MUX, "fmc_mux", fmc_mux_p, ARRAY_SIZE(fmc_mux_p),
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CLK_SET_RATE_PARENT, 0xc0, 2, 3, 0, fmc_mux_table, },
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{ HI3516CV300_MMC0_MUX, "mmc0_mux", mmc_mux_p, ARRAY_SIZE(mmc_mux_p),
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CLK_SET_RATE_PARENT, 0xc4, 4, 2, 0, mmc_mux_table, },
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{ HI3516CV300_MMC1_MUX, "mmc1_mux", mmc_mux_p, ARRAY_SIZE(mmc_mux_p),
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CLK_SET_RATE_PARENT, 0xc4, 12, 2, 0, mmc_mux_table, },
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{ HI3516CV300_MMC2_MUX, "mmc2_mux", mmc2_mux_p, ARRAY_SIZE(mmc2_mux_p),
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CLK_SET_RATE_PARENT, 0xc4, 20, 2, 0, mmc2_mux_table, },
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{ HI3516CV300_MMC3_MUX, "mmc3_mux", mmc_mux_p, ARRAY_SIZE(mmc_mux_p),
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CLK_SET_RATE_PARENT, 0xc8, 4, 2, 0, mmc_mux_table, },
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{ HI3516CV300_PWM_MUX, "pwm_mux", pwm_mux_p, ARRAY_SIZE(pwm_mux_p),
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CLK_SET_RATE_PARENT, 0x38, 2, 2, 0, pwm_mux_table, },
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};
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static const struct hisi_gate_clock hi3516cv300_gate_clks[] = {
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{ HI3516CV300_UART0_CLK, "clk_uart0", "uart_mux", CLK_SET_RATE_PARENT,
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0xe4, 15, 0, },
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{ HI3516CV300_UART1_CLK, "clk_uart1", "uart_mux", CLK_SET_RATE_PARENT,
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0xe4, 16, 0, },
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{ HI3516CV300_UART2_CLK, "clk_uart2", "uart_mux", CLK_SET_RATE_PARENT,
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0xe4, 17, 0, },
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{ HI3516CV300_SPI0_CLK, "clk_spi0", "100m", CLK_SET_RATE_PARENT,
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0xe4, 13, 0, },
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{ HI3516CV300_SPI1_CLK, "clk_spi1", "100m", CLK_SET_RATE_PARENT,
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0xe4, 14, 0, },
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{ HI3516CV300_FMC_CLK, "clk_fmc", "fmc_mux", CLK_SET_RATE_PARENT,
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0xc0, 1, 0, },
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{ HI3516CV300_MMC0_CLK, "clk_mmc0", "mmc0_mux", CLK_SET_RATE_PARENT,
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0xc4, 1, 0, },
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{ HI3516CV300_MMC1_CLK, "clk_mmc1", "mmc1_mux", CLK_SET_RATE_PARENT,
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0xc4, 9, 0, },
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{ HI3516CV300_MMC2_CLK, "clk_mmc2", "mmc2_mux", CLK_SET_RATE_PARENT,
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0xc4, 17, 0, },
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{ HI3516CV300_MMC3_CLK, "clk_mmc3", "mmc3_mux", CLK_SET_RATE_PARENT,
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0xc8, 1, 0, },
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{ HI3516CV300_ETH_CLK, "clk_eth", NULL, 0, 0xec, 1, 0, },
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{ HI3516CV300_DMAC_CLK, "clk_dmac", NULL, 0, 0xd8, 5, 0, },
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{ HI3516CV300_PWM_CLK, "clk_pwm", "pwm_mux", CLK_SET_RATE_PARENT,
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0x38, 1, 0, },
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{ HI3516CV300_USB2_BUS_CLK, "clk_usb2_bus", NULL, 0, 0xb8, 0, 0, },
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{ HI3516CV300_USB2_OHCI48M_CLK, "clk_usb2_ohci48m", NULL, 0,
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0xb8, 1, 0, },
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{ HI3516CV300_USB2_OHCI12M_CLK, "clk_usb2_ohci12m", NULL, 0,
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0xb8, 2, 0, },
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{ HI3516CV300_USB2_OTG_UTMI_CLK, "clk_usb2_otg_utmi", NULL, 0,
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0xb8, 3, 0, },
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{ HI3516CV300_USB2_HST_PHY_CLK, "clk_usb2_hst_phy", NULL, 0,
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0xb8, 4, 0, },
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{ HI3516CV300_USB2_UTMI0_CLK, "clk_usb2_utmi0", NULL, 0, 0xb8, 5, 0, },
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{ HI3516CV300_USB2_PHY_CLK, "clk_usb2_phy", NULL, 0, 0xb8, 7, 0, },
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};
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static struct hisi_clock_data *hi3516cv300_clk_register(
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struct platform_device *pdev)
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{
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struct hisi_clock_data *clk_data;
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int ret;
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clk_data = hisi_clk_alloc(pdev, HI3516CV300_CRG_NR_CLKS);
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if (!clk_data)
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return ERR_PTR(-ENOMEM);
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ret = hisi_clk_register_fixed_rate(hi3516cv300_fixed_rate_clks,
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ARRAY_SIZE(hi3516cv300_fixed_rate_clks), clk_data);
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if (ret)
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return ERR_PTR(ret);
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ret = hisi_clk_register_mux(hi3516cv300_mux_clks,
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ARRAY_SIZE(hi3516cv300_mux_clks), clk_data);
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if (ret)
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goto unregister_fixed_rate;
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ret = hisi_clk_register_gate(hi3516cv300_gate_clks,
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ARRAY_SIZE(hi3516cv300_gate_clks), clk_data);
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if (ret)
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goto unregister_mux;
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ret = of_clk_add_provider(pdev->dev.of_node,
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of_clk_src_onecell_get, &clk_data->clk_data);
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if (ret)
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goto unregister_gate;
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return clk_data;
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unregister_gate:
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hisi_clk_unregister_gate(hi3516cv300_gate_clks,
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ARRAY_SIZE(hi3516cv300_gate_clks), clk_data);
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unregister_mux:
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hisi_clk_unregister_mux(hi3516cv300_mux_clks,
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ARRAY_SIZE(hi3516cv300_mux_clks), clk_data);
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unregister_fixed_rate:
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hisi_clk_unregister_fixed_rate(hi3516cv300_fixed_rate_clks,
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ARRAY_SIZE(hi3516cv300_fixed_rate_clks), clk_data);
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return ERR_PTR(ret);
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}
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static void hi3516cv300_clk_unregister(struct platform_device *pdev)
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{
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struct hisi_crg_dev *crg = platform_get_drvdata(pdev);
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of_clk_del_provider(pdev->dev.of_node);
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hisi_clk_unregister_gate(hi3516cv300_gate_clks,
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ARRAY_SIZE(hi3516cv300_gate_clks), crg->clk_data);
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hisi_clk_unregister_mux(hi3516cv300_mux_clks,
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ARRAY_SIZE(hi3516cv300_mux_clks), crg->clk_data);
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hisi_clk_unregister_fixed_rate(hi3516cv300_fixed_rate_clks,
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ARRAY_SIZE(hi3516cv300_fixed_rate_clks), crg->clk_data);
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}
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static const struct hisi_crg_funcs hi3516cv300_crg_funcs = {
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.register_clks = hi3516cv300_clk_register,
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.unregister_clks = hi3516cv300_clk_unregister,
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};
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/* hi3516CV300 sysctrl CRG */
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#define HI3516CV300_SYSCTRL_NR_CLKS 16
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static const char *wdt_mux_p[] __initconst = { "3m", "apb" };
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static u32 wdt_mux_table[] = {0, 1};
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static const struct hisi_mux_clock hi3516cv300_sysctrl_mux_clks[] = {
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{ HI3516CV300_WDT_CLK, "wdt", wdt_mux_p, ARRAY_SIZE(wdt_mux_p),
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CLK_SET_RATE_PARENT, 0x0, 23, 1, 0, wdt_mux_table, },
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};
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static struct hisi_clock_data *hi3516cv300_sysctrl_clk_register(
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struct platform_device *pdev)
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{
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struct hisi_clock_data *clk_data;
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int ret;
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clk_data = hisi_clk_alloc(pdev, HI3516CV300_SYSCTRL_NR_CLKS);
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if (!clk_data)
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return ERR_PTR(-ENOMEM);
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ret = hisi_clk_register_mux(hi3516cv300_sysctrl_mux_clks,
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ARRAY_SIZE(hi3516cv300_sysctrl_mux_clks), clk_data);
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if (ret)
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return ERR_PTR(ret);
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ret = of_clk_add_provider(pdev->dev.of_node,
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of_clk_src_onecell_get, &clk_data->clk_data);
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if (ret)
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goto unregister_mux;
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return clk_data;
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unregister_mux:
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hisi_clk_unregister_mux(hi3516cv300_sysctrl_mux_clks,
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ARRAY_SIZE(hi3516cv300_sysctrl_mux_clks), clk_data);
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return ERR_PTR(ret);
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}
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static void hi3516cv300_sysctrl_clk_unregister(struct platform_device *pdev)
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{
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struct hisi_crg_dev *crg = platform_get_drvdata(pdev);
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of_clk_del_provider(pdev->dev.of_node);
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hisi_clk_unregister_mux(hi3516cv300_sysctrl_mux_clks,
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ARRAY_SIZE(hi3516cv300_sysctrl_mux_clks),
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crg->clk_data);
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}
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static const struct hisi_crg_funcs hi3516cv300_sysctrl_funcs = {
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.register_clks = hi3516cv300_sysctrl_clk_register,
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.unregister_clks = hi3516cv300_sysctrl_clk_unregister,
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};
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static const struct of_device_id hi3516cv300_crg_match_table[] = {
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{
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.compatible = "hisilicon,hi3516cv300-crg",
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.data = &hi3516cv300_crg_funcs
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},
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{
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.compatible = "hisilicon,hi3516cv300-sysctrl",
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.data = &hi3516cv300_sysctrl_funcs
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},
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{ }
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};
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MODULE_DEVICE_TABLE(of, hi3516cv300_crg_match_table);
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static int hi3516cv300_crg_probe(struct platform_device *pdev)
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{
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struct hisi_crg_dev *crg;
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crg = devm_kmalloc(&pdev->dev, sizeof(*crg), GFP_KERNEL);
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if (!crg)
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return -ENOMEM;
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crg->funcs = of_device_get_match_data(&pdev->dev);
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if (!crg->funcs)
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return -ENOENT;
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crg->rstc = hisi_reset_init(pdev);
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if (!crg->rstc)
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return -ENOMEM;
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crg->clk_data = crg->funcs->register_clks(pdev);
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if (IS_ERR(crg->clk_data)) {
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hisi_reset_exit(crg->rstc);
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return PTR_ERR(crg->clk_data);
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}
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platform_set_drvdata(pdev, crg);
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return 0;
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}
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static int hi3516cv300_crg_remove(struct platform_device *pdev)
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{
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struct hisi_crg_dev *crg = platform_get_drvdata(pdev);
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hisi_reset_exit(crg->rstc);
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crg->funcs->unregister_clks(pdev);
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return 0;
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}
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static struct platform_driver hi3516cv300_crg_driver = {
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.probe = hi3516cv300_crg_probe,
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.remove = hi3516cv300_crg_remove,
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.driver = {
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.name = "hi3516cv300-crg",
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.of_match_table = hi3516cv300_crg_match_table,
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},
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};
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static int __init hi3516cv300_crg_init(void)
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{
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return platform_driver_register(&hi3516cv300_crg_driver);
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}
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core_initcall(hi3516cv300_crg_init);
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static void __exit hi3516cv300_crg_exit(void)
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{
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platform_driver_unregister(&hi3516cv300_crg_driver);
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}
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module_exit(hi3516cv300_crg_exit);
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MODULE_LICENSE("GPL v2");
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MODULE_DESCRIPTION("HiSilicon Hi3516CV300 CRG Driver");
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