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https://github.com/edk2-porting/linux-next.git
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6205406cf6
Init field must be cleared in driver probe as this structure is not
dinamically allocated. If not, wrong flags can be passed to core.
Signed-off-by: Jose Abreu <joabreu@synopsys.com>
Cc: Carlos Palminha <palminha@synopsys.com>
Cc: Stephen Boyd <sboyd@codeaurora.org>
Cc: Michael Turquette <mturquette@baylibre.com>
Cc: linux-clk@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Fixes: 923587aafc
("clk/axs10x: Add I2S PLL clock driver")
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
Link: lkml.kernel.org/r/040cc9afdfa0e95ce7a01c406ff427ef7dc0c0fd.1481540717.git.joabreu@synopsys.com
230 lines
5.7 KiB
C
230 lines
5.7 KiB
C
/*
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* Synopsys AXS10X SDP I2S PLL clock driver
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*
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* Copyright (C) 2016 Synopsys
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#include <linux/platform_device.h>
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#include <linux/module.h>
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#include <linux/clk-provider.h>
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#include <linux/err.h>
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#include <linux/device.h>
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#include <linux/of_address.h>
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#include <linux/slab.h>
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#include <linux/of.h>
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/* PLL registers addresses */
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#define PLL_IDIV_REG 0x0
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#define PLL_FBDIV_REG 0x4
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#define PLL_ODIV0_REG 0x8
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#define PLL_ODIV1_REG 0xC
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struct i2s_pll_cfg {
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unsigned int rate;
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unsigned int idiv;
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unsigned int fbdiv;
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unsigned int odiv0;
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unsigned int odiv1;
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};
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static const struct i2s_pll_cfg i2s_pll_cfg_27m[] = {
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/* 27 Mhz */
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{ 1024000, 0x104, 0x451, 0x10E38, 0x2000 },
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{ 1411200, 0x104, 0x596, 0x10D35, 0x2000 },
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{ 1536000, 0x208, 0xA28, 0x10B2C, 0x2000 },
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{ 2048000, 0x82, 0x451, 0x10E38, 0x2000 },
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{ 2822400, 0x82, 0x596, 0x10D35, 0x2000 },
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{ 3072000, 0x104, 0xA28, 0x10B2C, 0x2000 },
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{ 2116800, 0x82, 0x3CF, 0x10C30, 0x2000 },
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{ 2304000, 0x104, 0x79E, 0x10B2C, 0x2000 },
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{ 0, 0, 0, 0, 0 },
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};
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static const struct i2s_pll_cfg i2s_pll_cfg_28m[] = {
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/* 28.224 Mhz */
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{ 1024000, 0x82, 0x105, 0x107DF, 0x2000 },
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{ 1411200, 0x28A, 0x1, 0x10001, 0x2000 },
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{ 1536000, 0xA28, 0x187, 0x10042, 0x2000 },
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{ 2048000, 0x41, 0x105, 0x107DF, 0x2000 },
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{ 2822400, 0x145, 0x1, 0x10001, 0x2000 },
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{ 3072000, 0x514, 0x187, 0x10042, 0x2000 },
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{ 2116800, 0x514, 0x42, 0x10001, 0x2000 },
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{ 2304000, 0x619, 0x82, 0x10001, 0x2000 },
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{ 0, 0, 0, 0, 0 },
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};
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struct i2s_pll_clk {
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void __iomem *base;
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struct clk_hw hw;
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struct device *dev;
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};
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static inline void i2s_pll_write(struct i2s_pll_clk *clk, unsigned int reg,
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unsigned int val)
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{
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writel_relaxed(val, clk->base + reg);
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}
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static inline unsigned int i2s_pll_read(struct i2s_pll_clk *clk,
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unsigned int reg)
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{
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return readl_relaxed(clk->base + reg);
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}
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static inline struct i2s_pll_clk *to_i2s_pll_clk(struct clk_hw *hw)
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{
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return container_of(hw, struct i2s_pll_clk, hw);
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}
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static inline unsigned int i2s_pll_get_value(unsigned int val)
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{
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return (val & 0x3F) + ((val >> 6) & 0x3F);
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}
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static const struct i2s_pll_cfg *i2s_pll_get_cfg(unsigned long prate)
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{
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switch (prate) {
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case 27000000:
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return i2s_pll_cfg_27m;
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case 28224000:
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return i2s_pll_cfg_28m;
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default:
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return NULL;
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}
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}
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static unsigned long i2s_pll_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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struct i2s_pll_clk *clk = to_i2s_pll_clk(hw);
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unsigned int idiv, fbdiv, odiv;
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idiv = i2s_pll_get_value(i2s_pll_read(clk, PLL_IDIV_REG));
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fbdiv = i2s_pll_get_value(i2s_pll_read(clk, PLL_FBDIV_REG));
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odiv = i2s_pll_get_value(i2s_pll_read(clk, PLL_ODIV0_REG));
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return ((parent_rate / idiv) * fbdiv) / odiv;
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}
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static long i2s_pll_round_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long *prate)
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{
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struct i2s_pll_clk *clk = to_i2s_pll_clk(hw);
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const struct i2s_pll_cfg *pll_cfg = i2s_pll_get_cfg(*prate);
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int i;
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if (!pll_cfg) {
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dev_err(clk->dev, "invalid parent rate=%ld\n", *prate);
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return -EINVAL;
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}
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for (i = 0; pll_cfg[i].rate != 0; i++)
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if (pll_cfg[i].rate == rate)
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return rate;
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return -EINVAL;
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}
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static int i2s_pll_set_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long parent_rate)
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{
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struct i2s_pll_clk *clk = to_i2s_pll_clk(hw);
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const struct i2s_pll_cfg *pll_cfg = i2s_pll_get_cfg(parent_rate);
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int i;
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if (!pll_cfg) {
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dev_err(clk->dev, "invalid parent rate=%ld\n", parent_rate);
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return -EINVAL;
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}
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for (i = 0; pll_cfg[i].rate != 0; i++) {
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if (pll_cfg[i].rate == rate) {
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i2s_pll_write(clk, PLL_IDIV_REG, pll_cfg[i].idiv);
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i2s_pll_write(clk, PLL_FBDIV_REG, pll_cfg[i].fbdiv);
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i2s_pll_write(clk, PLL_ODIV0_REG, pll_cfg[i].odiv0);
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i2s_pll_write(clk, PLL_ODIV1_REG, pll_cfg[i].odiv1);
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return 0;
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}
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}
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dev_err(clk->dev, "invalid rate=%ld, parent_rate=%ld\n", rate,
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parent_rate);
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return -EINVAL;
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}
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static const struct clk_ops i2s_pll_ops = {
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.recalc_rate = i2s_pll_recalc_rate,
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.round_rate = i2s_pll_round_rate,
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.set_rate = i2s_pll_set_rate,
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};
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static int i2s_pll_clk_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct device_node *node = dev->of_node;
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const char *clk_name;
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const char *parent_name;
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struct clk *clk;
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struct i2s_pll_clk *pll_clk;
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struct clk_init_data init;
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struct resource *mem;
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pll_clk = devm_kzalloc(dev, sizeof(*pll_clk), GFP_KERNEL);
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if (!pll_clk)
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return -ENOMEM;
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mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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pll_clk->base = devm_ioremap_resource(dev, mem);
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if (IS_ERR(pll_clk->base))
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return PTR_ERR(pll_clk->base);
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memset(&init, 0, sizeof(init));
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clk_name = node->name;
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init.name = clk_name;
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init.ops = &i2s_pll_ops;
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parent_name = of_clk_get_parent_name(node, 0);
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init.parent_names = &parent_name;
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init.num_parents = 1;
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pll_clk->hw.init = &init;
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pll_clk->dev = dev;
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clk = devm_clk_register(dev, &pll_clk->hw);
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if (IS_ERR(clk)) {
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dev_err(dev, "failed to register %s clock (%ld)\n",
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clk_name, PTR_ERR(clk));
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return PTR_ERR(clk);
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}
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return of_clk_add_provider(node, of_clk_src_simple_get, clk);
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}
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static int i2s_pll_clk_remove(struct platform_device *pdev)
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{
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of_clk_del_provider(pdev->dev.of_node);
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return 0;
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}
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static const struct of_device_id i2s_pll_clk_id[] = {
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{ .compatible = "snps,axs10x-i2s-pll-clock", },
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{ },
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};
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MODULE_DEVICE_TABLE(of, i2s_pll_clk_id);
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static struct platform_driver i2s_pll_clk_driver = {
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.driver = {
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.name = "axs10x-i2s-pll-clock",
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.of_match_table = i2s_pll_clk_id,
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},
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.probe = i2s_pll_clk_probe,
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.remove = i2s_pll_clk_remove,
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};
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module_platform_driver(i2s_pll_clk_driver);
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MODULE_AUTHOR("Jose Abreu <joabreu@synopsys.com>");
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MODULE_DESCRIPTION("Synopsys AXS10X SDP I2S PLL Clock Driver");
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MODULE_LICENSE("GPL v2");
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