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d3ce7f2594
This commit adds the basic support for the Armada 375 SOCs. These SoCs share most of their IP with the Armada 370/XP SoCs. The main difference is the use of a Cortex A9 CPU instead of the PJ4B CPU. The interrupt controller and the L2 cache controller are also different they are respectively the GIC and the PL310. The support is introduced in board-v7.c, together with Armada 370/XP, but a separate DT structure is added, because Armada 375 will need a different set of SMP operations when the SMP support is introduced. Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
10 lines
263 B
Plaintext
10 lines
263 B
Plaintext
Marvell Armada 375 Platforms Device Tree Bindings
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Boards with a SoC of the Marvell Armada 375 family shall have the
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following property:
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Required root node property:
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compatible: must contain "marvell,armada375"
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