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Date: From: Mauro Carvalho Chehab <mchehab@infradead.org> There are some docs at V4L/DVB tree that were never included at kernel. This patch includes those docs. Signed-off-by: Mauro Carvalho Chehab <mchehab@infradead.org>
50 lines
2.1 KiB
Plaintext
50 lines
2.1 KiB
Plaintext
This document describes how to upload the cx2341x firmware to the card.
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How to find
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===========
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See the web pages of the various projects that uses this chip for information
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on how to obtain the firmware.
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The firmware stored in a Windows driver can be detected as follows:
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- Each firmware image is 256k bytes.
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- The 1st 32-bit word of the Encoder image is 0x0000da7
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- The 1st 32-bit word of the Decoder image is 0x00003a7
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- The 2nd 32-bit word of both images is 0xaa55bb66
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How to load
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===========
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- Issue the FWapi command to stop the encoder if it is running. Wait for the
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command to complete.
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- Issue the FWapi command to stop the decoder if it is running. Wait for the
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command to complete.
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- Issue the I2C command to the digitizer to stop emitting VSYNC events.
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- Issue the FWapi command to halt the encoder's firmware.
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- Sleep for 10ms.
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- Issue the FWapi command to halt the decoder's firmware.
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- Sleep for 10ms.
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- Write 0x00000000 to register 0x2800 to stop the Video Display Module.
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- Write 0x00000005 to register 0x2D00 to stop the AO (audio output?).
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- Write 0x00000000 to register 0xA064 to ping? the APU.
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- Write 0xFFFFFFFE to register 0x9058 to stop the VPU.
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- Write 0xFFFFFFFF to register 0x9054 to reset the HW blocks.
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- Write 0x00000001 to register 0x9050 to stop the SPU.
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- Sleep for 10ms.
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- Write 0x0000001A to register 0x07FC to init the Encoder SDRAM's pre-charge.
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- Write 0x80000640 to register 0x07F8 to init the Encoder SDRAM's refresh to 1us.
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- Write 0x0000001A to register 0x08FC to init the Decoder SDRAM's pre-charge.
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- Write 0x80000640 to register 0x08F8 to init the Decoder SDRAM's refresh to 1us.
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- Sleep for 512ms. (600ms is recommended)
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- Transfer the encoder's firmware image to offset 0 in Encoder memory space.
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- Transfer the decoder's firmware image to offset 0 in Decoder memory space.
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- Use a read-modify-write operation to Clear bit 0 of register 0x9050 to
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re-enable the SPU.
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- Sleep for 1 second.
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- Use a read-modify-write operation to Clear bits 3 and 0 of register 0x9058
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to re-enable the VPU.
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- Sleep for 1 second.
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- Issue status API commands to both firmware images to verify.
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