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0b33162ec5
This is a series from Arnd that fixes a number of compiler warnings when building defconfigs on ARM. * late/fixes: ARM: footbridge: nw_gpio_lock is raw_spin_lock ARM: mv78xx0: correct addr_map_cfg __initdata annotation ARM: footbridge: remove RTC_IRQ definition ARM: soc: dependency warnings for errata ARM: ks8695: __arch_virt_to_dma type handling ARM: rpc: check device_register return code in ecard_probe ARM: davinci: don't mark da850_register_cpufreq as __init ARM: iop13xx: fix iq81340sc_atux_map_irq prototype ARM: iop13xx: mark iop13xx_scan_bus as __devinit ARM: mv78xx0: mark mv78xx0_timer_init as __init_refok ARM: s3c24xx: fix multiple section mismatch warnings ARM: at91: unused variable in at91_pm_verify_clocks ARM: at91: skip at91_io_desc definition for NOMMU ARM: pxa: work around duplicate definition of GPIO24_SSP1_SFRM ARM: pxa: remove sharpsl_fatal_check function ARM: pxa: define palmte2_pxa_keys conditionally ARM: pxa: Wunused-result warning in viper board file ARM: shark: fix shark_pci_init return code Fixed trivial conflicts in arch/arm/mach-at91/setup.c. Signed-off-by: Olof Johansson <olof@lixom.net>
94 lines
2.4 KiB
C
94 lines
2.4 KiB
C
/*
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* arch/arm/mach-mv78xx0/addr-map.c
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*
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* Address map functions for Marvell MV78xx0 SoCs
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/mbus.h>
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#include <linux/io.h>
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#include <plat/addr-map.h>
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#include <mach/mv78xx0.h>
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#include "common.h"
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/*
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* Generic Address Decode Windows bit settings
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*/
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#define TARGET_DEV_BUS 1
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#define TARGET_PCIE0 4
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#define TARGET_PCIE1 8
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#define TARGET_PCIE(i) ((i) ? TARGET_PCIE1 : TARGET_PCIE0)
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#define ATTR_DEV_SPI_ROM 0x1f
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#define ATTR_DEV_BOOT 0x2f
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#define ATTR_DEV_CS3 0x37
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#define ATTR_DEV_CS2 0x3b
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#define ATTR_DEV_CS1 0x3d
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#define ATTR_DEV_CS0 0x3e
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#define ATTR_PCIE_IO(l) (0xf0 & ~(0x10 << (l)))
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#define ATTR_PCIE_MEM(l) (0xf8 & ~(0x10 << (l)))
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/*
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* CPU Address Decode Windows registers
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*/
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#define WIN0_OFF(n) (BRIDGE_VIRT_BASE + 0x0000 + ((n) << 4))
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#define WIN8_OFF(n) (BRIDGE_VIRT_BASE + 0x0900 + (((n) - 8) << 4))
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static void __init __iomem *win_cfg_base(const struct orion_addr_map_cfg *cfg, int win)
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{
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/*
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* Find the control register base address for this window.
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*
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* BRIDGE_VIRT_BASE points to the right (CPU0's or CPU1's)
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* MBUS bridge depending on which CPU core we're running on,
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* so we don't need to take that into account here.
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*/
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return (win < 8) ? WIN0_OFF(win) : WIN8_OFF(win);
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}
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/*
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* Description of the windows needed by the platform code
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*/
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static struct orion_addr_map_cfg addr_map_cfg __initdata = {
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.num_wins = 14,
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.remappable_wins = 8,
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.win_cfg_base = win_cfg_base,
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};
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void __init mv78xx0_setup_cpu_mbus(void)
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{
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/*
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* Disable, clear and configure windows.
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*/
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orion_config_wins(&addr_map_cfg, NULL);
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/*
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* Setup MBUS dram target info.
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*/
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if (mv78xx0_core_index() == 0)
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orion_setup_cpu_mbus_target(&addr_map_cfg,
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(void __iomem *) DDR_WINDOW_CPU0_BASE);
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else
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orion_setup_cpu_mbus_target(&addr_map_cfg,
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(void __iomem *) DDR_WINDOW_CPU1_BASE);
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}
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void __init mv78xx0_setup_pcie_io_win(int window, u32 base, u32 size,
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int maj, int min)
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{
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orion_setup_cpu_win(&addr_map_cfg, window, base, size,
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TARGET_PCIE(maj), ATTR_PCIE_IO(min), 0);
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}
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void __init mv78xx0_setup_pcie_mem_win(int window, u32 base, u32 size,
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int maj, int min)
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{
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orion_setup_cpu_win(&addr_map_cfg, window, base, size,
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TARGET_PCIE(maj), ATTR_PCIE_MEM(min), -1);
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}
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