mirror of
https://github.com/edk2-porting/linux-next.git
synced 2024-12-19 18:53:52 +08:00
520f7bd733
Now that we have GIC moved to drivers/irqchip and all GIC DT init for platforms using irqchip_init, move gic.h and update the remaining includes. Signed-off-by: Rob Herring <rob.herring@calxeda.com> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Russell King <linux@arm.linux.org.uk> Cc: Anton Vorontsov <avorontsov@mvista.com> Cc: Kukjin Kim <kgene.kim@samsung.com> Cc: Sascha Hauer <kernel@pengutronix.de> Cc: David Brown <davidb@codeaurora.org> Cc: Daniel Walker <dwalker@fifo99.com> Cc: Bryan Huntsman <bryanh@codeaurora.org> Cc: Tony Lindgren <tony@atomide.com> Cc: Paul Mundt <lethal@linux-sh.org> Cc: Magnus Damm <magnus.damm@gmail.com> Cc: Viresh Kumar <viresh.linux@gmail.com> Cc: Shiraz Hashim <shiraz.hashim@st.com> Cc: Stephen Warren <swarren@wwwdotorg.org> Cc: Srinidhi Kasagar <srinidhi.kasagar@stericsson.com> Cc: Linus Walleij <linus.walleij@linaro.org> Cc: Samuel Ortiz <sameo@linux.intel.com>
147 lines
3.7 KiB
C
147 lines
3.7 KiB
C
/*
|
|
* SMP support for R-Mobile / SH-Mobile - sh73a0 portion
|
|
*
|
|
* Copyright (C) 2010 Magnus Damm
|
|
* Copyright (C) 2010 Takashi Yoshii
|
|
*
|
|
* This program is free software; you can redistribute it and/or modify
|
|
* it under the terms of the GNU General Public License as published by
|
|
* the Free Software Foundation; version 2 of the License.
|
|
*
|
|
* This program is distributed in the hope that it will be useful,
|
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
* GNU General Public License for more details.
|
|
*
|
|
* You should have received a copy of the GNU General Public License
|
|
* along with this program; if not, write to the Free Software
|
|
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
|
*/
|
|
#include <linux/kernel.h>
|
|
#include <linux/init.h>
|
|
#include <linux/smp.h>
|
|
#include <linux/spinlock.h>
|
|
#include <linux/io.h>
|
|
#include <linux/delay.h>
|
|
#include <linux/irqchip/arm-gic.h>
|
|
#include <mach/common.h>
|
|
#include <asm/smp_plat.h>
|
|
#include <mach/sh73a0.h>
|
|
#include <asm/smp_scu.h>
|
|
#include <asm/smp_twd.h>
|
|
|
|
#define WUPCR IOMEM(0xe6151010)
|
|
#define SRESCR IOMEM(0xe6151018)
|
|
#define PSTR IOMEM(0xe6151040)
|
|
#define SBAR IOMEM(0xe6180020)
|
|
#define APARMBAREA IOMEM(0xe6f10020)
|
|
|
|
static void __iomem *scu_base_addr(void)
|
|
{
|
|
return (void __iomem *)0xf0000000;
|
|
}
|
|
|
|
static DEFINE_SPINLOCK(scu_lock);
|
|
static unsigned long tmp;
|
|
|
|
#ifdef CONFIG_HAVE_ARM_TWD
|
|
static DEFINE_TWD_LOCAL_TIMER(twd_local_timer, 0xf0000600, 29);
|
|
void __init sh73a0_register_twd(void)
|
|
{
|
|
twd_local_timer_register(&twd_local_timer);
|
|
}
|
|
#endif
|
|
|
|
static void modify_scu_cpu_psr(unsigned long set, unsigned long clr)
|
|
{
|
|
void __iomem *scu_base = scu_base_addr();
|
|
|
|
spin_lock(&scu_lock);
|
|
tmp = __raw_readl(scu_base + 8);
|
|
tmp &= ~clr;
|
|
tmp |= set;
|
|
spin_unlock(&scu_lock);
|
|
|
|
/* disable cache coherency after releasing the lock */
|
|
__raw_writel(tmp, scu_base + 8);
|
|
}
|
|
|
|
static unsigned int __init sh73a0_get_core_count(void)
|
|
{
|
|
void __iomem *scu_base = scu_base_addr();
|
|
|
|
return scu_get_core_count(scu_base);
|
|
}
|
|
|
|
static void __cpuinit sh73a0_secondary_init(unsigned int cpu)
|
|
{
|
|
gic_secondary_init(0);
|
|
}
|
|
|
|
static int __cpuinit sh73a0_boot_secondary(unsigned int cpu, struct task_struct *idle)
|
|
{
|
|
cpu = cpu_logical_map(cpu);
|
|
|
|
/* enable cache coherency */
|
|
modify_scu_cpu_psr(0, 3 << (cpu * 8));
|
|
|
|
if (((__raw_readl(PSTR) >> (4 * cpu)) & 3) == 3)
|
|
__raw_writel(1 << cpu, WUPCR); /* wake up */
|
|
else
|
|
__raw_writel(1 << cpu, SRESCR); /* reset */
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void __init sh73a0_smp_prepare_cpus(unsigned int max_cpus)
|
|
{
|
|
int cpu = cpu_logical_map(0);
|
|
|
|
scu_enable(scu_base_addr());
|
|
|
|
/* Map the reset vector (in headsmp.S) */
|
|
__raw_writel(0, APARMBAREA); /* 4k */
|
|
__raw_writel(__pa(shmobile_secondary_vector), SBAR);
|
|
|
|
/* enable cache coherency on CPU0 */
|
|
modify_scu_cpu_psr(0, 3 << (cpu * 8));
|
|
}
|
|
|
|
static void __init sh73a0_smp_init_cpus(void)
|
|
{
|
|
unsigned int ncores = sh73a0_get_core_count();
|
|
|
|
shmobile_smp_init_cpus(ncores);
|
|
}
|
|
|
|
static int __maybe_unused sh73a0_cpu_kill(unsigned int cpu)
|
|
{
|
|
int k;
|
|
|
|
/* this function is running on another CPU than the offline target,
|
|
* here we need wait for shutdown code in platform_cpu_die() to
|
|
* finish before asking SoC-specific code to power off the CPU core.
|
|
*/
|
|
for (k = 0; k < 1000; k++) {
|
|
if (shmobile_cpu_is_dead(cpu))
|
|
return 1;
|
|
|
|
mdelay(1);
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
|
|
struct smp_operations sh73a0_smp_ops __initdata = {
|
|
.smp_init_cpus = sh73a0_smp_init_cpus,
|
|
.smp_prepare_cpus = sh73a0_smp_prepare_cpus,
|
|
.smp_secondary_init = sh73a0_secondary_init,
|
|
.smp_boot_secondary = sh73a0_boot_secondary,
|
|
#ifdef CONFIG_HOTPLUG_CPU
|
|
.cpu_kill = sh73a0_cpu_kill,
|
|
.cpu_die = shmobile_cpu_die,
|
|
.cpu_disable = shmobile_cpu_disable,
|
|
#endif
|
|
};
|