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https://github.com/edk2-porting/linux-next.git
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bd3d924d71
The SRC in i.MX51 and i.MX53 is similar to the one in i.MX6q minus the IPU2 reset line and multi core CPU reset/enable bits. Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> Reviewed-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Pavel Machek <pavel@ucw.cz> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
164 lines
4.4 KiB
C
164 lines
4.4 KiB
C
/*
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* Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
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*
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* The code contained herein is licensed under the GNU General Public
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* License. You may obtain a copy of the GNU General Public License
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* Version 2 or later at the following locations:
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*
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* http://www.opensource.org/licenses/gpl-license.html
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* http://www.gnu.org/copyleft/gpl.html
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*
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* Create static mapping between physical to virtual memory.
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*/
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#include <linux/mm.h>
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#include <linux/init.h>
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#include <linux/clk.h>
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#include <linux/pinctrl/machine.h>
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#include <asm/mach/map.h>
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#include "common.h"
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#include "devices/devices-common.h"
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#include "hardware.h"
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#include "iomux-v3.h"
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/*
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* Define the MX51 memory map.
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*/
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static struct map_desc mx51_io_desc[] __initdata = {
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imx_map_entry(MX51, TZIC, MT_DEVICE),
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imx_map_entry(MX51, IRAM, MT_DEVICE),
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imx_map_entry(MX51, AIPS1, MT_DEVICE),
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imx_map_entry(MX51, SPBA0, MT_DEVICE),
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imx_map_entry(MX51, AIPS2, MT_DEVICE),
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};
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/*
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* Define the MX53 memory map.
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*/
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static struct map_desc mx53_io_desc[] __initdata = {
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imx_map_entry(MX53, TZIC, MT_DEVICE),
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imx_map_entry(MX53, AIPS1, MT_DEVICE),
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imx_map_entry(MX53, SPBA0, MT_DEVICE),
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imx_map_entry(MX53, AIPS2, MT_DEVICE),
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};
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/*
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* This function initializes the memory map. It is called during the
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* system startup to create static physical to virtual memory mappings
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* for the IO modules.
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*/
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void __init mx51_map_io(void)
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{
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iotable_init(mx51_io_desc, ARRAY_SIZE(mx51_io_desc));
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}
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void __init mx53_map_io(void)
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{
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iotable_init(mx53_io_desc, ARRAY_SIZE(mx53_io_desc));
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}
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/*
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* The MIPI HSC unit has been removed from the i.MX51 Reference Manual by
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* the Freescale marketing division. However this did not remove the
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* hardware from the chip which still needs to be configured for proper
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* IPU support.
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*/
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static void __init imx51_ipu_mipi_setup(void)
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{
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void __iomem *hsc_addr;
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hsc_addr = MX51_IO_ADDRESS(MX51_MIPI_HSC_BASE_ADDR);
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/* setup MIPI module to legacy mode */
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__raw_writel(0xf00, hsc_addr);
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/* CSI mode: reserved; DI control mode: legacy (from Freescale BSP) */
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__raw_writel(__raw_readl(hsc_addr + 0x800) | 0x30ff,
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hsc_addr + 0x800);
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}
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void __init imx51_init_early(void)
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{
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imx51_ipu_mipi_setup();
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mxc_set_cpu_type(MXC_CPU_MX51);
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mxc_iomux_v3_init(MX51_IO_ADDRESS(MX51_IOMUXC_BASE_ADDR));
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mxc_arch_reset_init(MX51_IO_ADDRESS(MX51_WDOG1_BASE_ADDR));
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imx_src_init();
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}
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void __init imx53_init_early(void)
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{
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mxc_set_cpu_type(MXC_CPU_MX53);
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mxc_iomux_v3_init(MX53_IO_ADDRESS(MX53_IOMUXC_BASE_ADDR));
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mxc_arch_reset_init(MX53_IO_ADDRESS(MX53_WDOG1_BASE_ADDR));
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imx_src_init();
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}
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void __init mx51_init_irq(void)
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{
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tzic_init_irq(MX51_IO_ADDRESS(MX51_TZIC_BASE_ADDR));
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}
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void __init mx53_init_irq(void)
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{
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tzic_init_irq(MX53_IO_ADDRESS(MX53_TZIC_BASE_ADDR));
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}
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static struct sdma_script_start_addrs imx51_sdma_script __initdata = {
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.ap_2_ap_addr = 642,
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.uart_2_mcu_addr = 817,
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.mcu_2_app_addr = 747,
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.mcu_2_shp_addr = 961,
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.ata_2_mcu_addr = 1473,
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.mcu_2_ata_addr = 1392,
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.app_2_per_addr = 1033,
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.app_2_mcu_addr = 683,
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.shp_2_per_addr = 1251,
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.shp_2_mcu_addr = 892,
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};
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static struct sdma_platform_data imx51_sdma_pdata __initdata = {
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.fw_name = "sdma-imx51.bin",
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.script_addrs = &imx51_sdma_script,
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};
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static const struct resource imx51_audmux_res[] __initconst = {
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DEFINE_RES_MEM(MX51_AUDMUX_BASE_ADDR, SZ_16K),
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};
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void __init imx51_soc_init(void)
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{
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mxc_device_init();
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/* i.mx51 has the i.mx35 type gpio */
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mxc_register_gpio("imx35-gpio", 0, MX51_GPIO1_BASE_ADDR, SZ_16K, MX51_INT_GPIO1_LOW, MX51_INT_GPIO1_HIGH);
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mxc_register_gpio("imx35-gpio", 1, MX51_GPIO2_BASE_ADDR, SZ_16K, MX51_INT_GPIO2_LOW, MX51_INT_GPIO2_HIGH);
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mxc_register_gpio("imx35-gpio", 2, MX51_GPIO3_BASE_ADDR, SZ_16K, MX51_INT_GPIO3_LOW, MX51_INT_GPIO3_HIGH);
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mxc_register_gpio("imx35-gpio", 3, MX51_GPIO4_BASE_ADDR, SZ_16K, MX51_INT_GPIO4_LOW, MX51_INT_GPIO4_HIGH);
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pinctrl_provide_dummies();
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/* i.mx51 has the i.mx35 type sdma */
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imx_add_imx_sdma("imx35-sdma", MX51_SDMA_BASE_ADDR, MX51_INT_SDMA, &imx51_sdma_pdata);
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/* Setup AIPS registers */
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imx_set_aips(MX51_IO_ADDRESS(MX51_AIPS1_BASE_ADDR));
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imx_set_aips(MX51_IO_ADDRESS(MX51_AIPS2_BASE_ADDR));
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/* i.mx51 has the i.mx31 type audmux */
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platform_device_register_simple("imx31-audmux", 0, imx51_audmux_res,
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ARRAY_SIZE(imx51_audmux_res));
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}
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void __init imx51_init_late(void)
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{
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mx51_neon_fixup();
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imx51_pm_init();
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}
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void __init imx53_init_late(void)
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{
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imx53_pm_init();
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}
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