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b47eb0eb9b
Signed-off-by: Chas Williams <chas@cmf.nrl.navy.mil> Signed-off-by: David S. Miller <davem@davemloft.net>
92 lines
3.7 KiB
C
92 lines
3.7 KiB
C
/* drivers/atm/idt77105.h - IDT77105 (PHY) declarations */
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/* Written 1999 by Greg Banks, NEC Australia <gnb@linuxfan.com>. Based on suni.h */
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#ifndef DRIVER_ATM_IDT77105_H
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#define DRIVER_ATM_IDT77105_H
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#include <linux/atmdev.h>
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#include <linux/atmioc.h>
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/* IDT77105 registers */
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#define IDT77105_MCR 0x0 /* Master Control Register */
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#define IDT77105_ISTAT 0x1 /* Interrupt Status */
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#define IDT77105_DIAG 0x2 /* Diagnostic Control */
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#define IDT77105_LEDHEC 0x3 /* LED Driver & HEC Status/Control */
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#define IDT77105_CTRLO 0x4 /* Low Byte Counter Register */
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#define IDT77105_CTRHI 0x5 /* High Byte Counter Register */
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#define IDT77105_CTRSEL 0x6 /* Counter Register Read Select */
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/* IDT77105 register values */
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/* MCR */
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#define IDT77105_MCR_UPLO 0x80 /* R/W, User Prog'le Output Latch */
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#define IDT77105_MCR_DREC 0x40 /* R/W, Discard Receive Error Cells */
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#define IDT77105_MCR_ECEIO 0x20 /* R/W, Enable Cell Error Interrupts
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* Only */
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#define IDT77105_MCR_TDPC 0x10 /* R/W, Transmit Data Parity Check */
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#define IDT77105_MCR_DRIC 0x08 /* R/W, Discard Received Idle Cells */
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#define IDT77105_MCR_HALTTX 0x04 /* R/W, Halt Tx */
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#define IDT77105_MCR_UMODE 0x02 /* R/W, Utopia (cell/byte) Mode */
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#define IDT77105_MCR_EIP 0x01 /* R/W, Enable Interrupt Pin */
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/* ISTAT */
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#define IDT77105_ISTAT_GOODSIG 0x40 /* R, Good Signal Bit */
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#define IDT77105_ISTAT_HECERR 0x20 /* sticky, HEC Error*/
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#define IDT77105_ISTAT_SCR 0x10 /* sticky, Short Cell Received */
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#define IDT77105_ISTAT_TPE 0x08 /* sticky, Transmit Parity Error */
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#define IDT77105_ISTAT_RSCC 0x04 /* sticky, Rx Signal Condition Change */
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#define IDT77105_ISTAT_RSE 0x02 /* sticky, Rx Symbol Error */
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#define IDT77105_ISTAT_RFO 0x01 /* sticky, Rx FIFO Overrun */
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/* DIAG */
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#define IDT77105_DIAG_FTD 0x80 /* R/W, Force TxClav deassert */
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#define IDT77105_DIAG_ROS 0x40 /* R/W, RxClav operation select */
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#define IDT77105_DIAG_MPCS 0x20 /* R/W, Multi-PHY config'n select */
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#define IDT77105_DIAG_RFLUSH 0x10 /* R/W, clear receive FIFO */
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#define IDT77105_DIAG_ITPE 0x08 /* R/W, Insert Tx payload error */
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#define IDT77105_DIAG_ITHE 0x04 /* R/W, Insert Tx HEC error */
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#define IDT77105_DIAG_UMODE 0x02 /* R/W, Utopia (cell/byte) Mode */
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#define IDT77105_DIAG_LCMASK 0x03 /* R/W, Loopback Control */
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#define IDT77105_DIAG_LC_NORMAL 0x00 /* Receive from network */
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#define IDT77105_DIAG_LC_PHY_LOOPBACK 0x02
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#define IDT77105_DIAG_LC_LINE_LOOPBACK 0x03
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/* LEDHEC */
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#define IDT77105_LEDHEC_DRHC 0x40 /* R/W, Disable Rx HEC check */
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#define IDT77105_LEDHEC_DTHC 0x20 /* R/W, Disable Tx HEC calculation */
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#define IDT77105_LEDHEC_RPWMASK 0x18 /* R/W, RxRef pulse width select */
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#define IDT77105_LEDHEC_TFS 0x04 /* R, Tx FIFO Status (1=empty) */
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#define IDT77105_LEDHEC_TLS 0x02 /* R, Tx LED Status (1=lit) */
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#define IDT77105_LEDHEC_RLS 0x01 /* R, Rx LED Status (1=lit) */
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#define IDT77105_LEDHEC_RPW_1 0x00 /* RxRef active for 1 RxClk cycle */
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#define IDT77105_LEDHEC_RPW_2 0x08 /* RxRef active for 2 RxClk cycle */
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#define IDT77105_LEDHEC_RPW_4 0x10 /* RxRef active for 4 RxClk cycle */
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#define IDT77105_LEDHEC_RPW_8 0x18 /* RxRef active for 8 RxClk cycle */
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/* CTRSEL */
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#define IDT77105_CTRSEL_SEC 0x08 /* W, Symbol Error Counter */
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#define IDT77105_CTRSEL_TCC 0x04 /* W, Tx Cell Counter */
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#define IDT77105_CTRSEL_RCC 0x02 /* W, Rx Cell Counter */
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#define IDT77105_CTRSEL_RHEC 0x01 /* W, Rx HEC Error Counter */
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#ifdef __KERNEL__
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int idt77105_init(struct atm_dev *dev);
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#endif
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/*
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* Tunable parameters
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*/
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/* Time between samples of the hardware cell counters. Should be <= 1 sec */
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#define IDT77105_STATS_TIMER_PERIOD (HZ)
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/* Time between checks to see if the signal has been found again */
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#define IDT77105_RESTART_TIMER_PERIOD (5 * HZ)
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#endif
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