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70f7cb78ec
This patch adds a driver for the MLC NAND controller of the LPC32xx SoC. [dwmw2: 21st century pedantry] Signed-off-by: Roland Stigge <stigge@antcom.de> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
51 lines
1.2 KiB
Plaintext
51 lines
1.2 KiB
Plaintext
NXP LPC32xx SoC NAND MLC controller
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Required properties:
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- compatible: "nxp,lpc3220-mlc"
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- reg: Address and size of the controller
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- interrupts: The NAND interrupt specification
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- gpios: GPIO specification for NAND write protect
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The following required properties are very controller specific. See the LPC32xx
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User Manual 7.5.14 MLC NAND Timing Register (the values here are specified in
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Hz, to make them independent of actual clock speed and to provide for good
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accuracy:)
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- nxp,tcea_delay: TCEA_DELAY
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- nxp,busy_delay: BUSY_DELAY
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- nxp,nand_ta: NAND_TA
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- nxp,rd_high: RD_HIGH
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- nxp,rd_low: RD_LOW
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- nxp,wr_high: WR_HIGH
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- nxp,wr_low: WR_LOW
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Optional subnodes:
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- Partitions, see Documentation/devicetree/bindings/mtd/partition.txt
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Example:
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mlc: flash@200A8000 {
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compatible = "nxp,lpc3220-mlc";
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reg = <0x200A8000 0x11000>;
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interrupts = <11 0>;
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#address-cells = <1>;
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#size-cells = <1>;
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nxp,tcea-delay = <333333333>;
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nxp,busy-delay = <10000000>;
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nxp,nand-ta = <18181818>;
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nxp,rd-high = <31250000>;
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nxp,rd-low = <45454545>;
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nxp,wr-high = <40000000>;
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nxp,wr-low = <83333333>;
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gpios = <&gpio 5 19 1>; /* GPO_P3 19, active low */
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mtd0@00000000 {
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label = "boot";
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reg = <0x00000000 0x00064000>;
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read-only;
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};
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...
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};
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