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c32da02342
* 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/jikos/trivial: (56 commits) doc: fix typo in comment explaining rb_tree usage Remove fs/ntfs/ChangeLog doc: fix console doc typo doc: cpuset: Update the cpuset flag file Fix of spelling in arch/sparc/kernel/leon_kernel.c no longer needed Remove drivers/parport/ChangeLog Remove drivers/char/ChangeLog doc: typo - Table 1-2 should refer to "status", not "statm" tree-wide: fix typos "ass?o[sc]iac?te" -> "associate" in comments No need to patch AMD-provided drivers/gpu/drm/radeon/atombios.h devres/irq: Fix devm_irq_match comment Remove reference to kthread_create_on_cpu tree-wide: Assorted spelling fixes tree-wide: fix 'lenght' typo in comments and code drm/kms: fix spelling in error message doc: capitalization and other minor fixes in pnp doc devres: typo fix s/dev/devm/ Remove redundant trailing semicolons from macros fix typo "definetly" -> "definitely" in comment tree-wide: s/widht/width/g typo in comments ... Fix trivial conflict in Documentation/laptops/00-INDEX
51 lines
1.6 KiB
C
51 lines
1.6 KiB
C
/* arch/arm/plat-s3c/include/plat/regs-usb-hsotg-phy.h
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*
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* Copyright 2008 Openmoko, Inc.
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* Copyright 2008 Simtec Electronics
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* http://armlinux.simtec.co.uk/
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* Ben Dooks <ben@simtec.co.uk>
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*
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* S3C - USB2.0 Highspeed/OtG device PHY registers
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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/* Note, this is a separate header file as some of the clock framework
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* needs to touch this if the clk_48m is used as the USB OHCI or other
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* peripheral source.
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*/
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#ifndef __PLAT_S3C64XX_REGS_USB_HSOTG_PHY_H
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#define __PLAT_S3C64XX_REGS_USB_HSOTG_PHY_H __FILE__
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/* S3C64XX_PA_USB_HSPHY */
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#define S3C_HSOTG_PHYREG(x) ((x) + S3C_VA_USB_HSPHY)
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#define S3C_PHYPWR S3C_HSOTG_PHYREG(0x00)
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#define SRC_PHYPWR_OTG_DISABLE (1 << 4)
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#define SRC_PHYPWR_ANALOG_POWERDOWN (1 << 3)
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#define SRC_PHYPWR_FORCE_SUSPEND (1 << 1)
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#define S3C_PHYCLK S3C_HSOTG_PHYREG(0x04)
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#define S3C_PHYCLK_MODE_USB11 (1 << 6)
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#define S3C_PHYCLK_EXT_OSC (1 << 5)
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#define S3C_PHYCLK_CLK_FORCE (1 << 4)
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#define S3C_PHYCLK_ID_PULL (1 << 2)
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#define S3C_PHYCLK_CLKSEL_MASK (0x3 << 0)
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#define S3C_PHYCLK_CLKSEL_SHIFT (0)
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#define S3C_PHYCLK_CLKSEL_48M (0x0 << 0)
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#define S3C_PHYCLK_CLKSEL_12M (0x2 << 0)
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#define S3C_PHYCLK_CLKSEL_24M (0x3 << 0)
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#define S3C_RSTCON S3C_HSOTG_PHYREG(0x08)
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#define S3C_RSTCON_PHYCLK (1 << 2)
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#define S3C_RSTCON_HCLK (1 << 2)
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#define S3C_RSTCON_PHY (1 << 0)
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#define S3C_PHYTUNE S3C_HSOTG_PHYREG(0x20)
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#endif /* __PLAT_S3C64XX_REGS_USB_HSOTG_PHY_H */
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