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099a480913
The smp_scu driver needs to use the relaxed readl/write accessors to avoid any issues with the endian mode the processor core is in. Reviewed-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk>
89 lines
2.1 KiB
C
89 lines
2.1 KiB
C
/*
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* linux/arch/arm/kernel/smp_scu.c
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*
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* Copyright (C) 2002 ARM Ltd.
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* All Rights Reserved
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/init.h>
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#include <linux/io.h>
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#include <asm/smp_plat.h>
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#include <asm/smp_scu.h>
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#include <asm/cacheflush.h>
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#include <asm/cputype.h>
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#define SCU_CTRL 0x00
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#define SCU_CONFIG 0x04
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#define SCU_CPU_STATUS 0x08
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#define SCU_INVALIDATE 0x0c
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#define SCU_FPGA_REVISION 0x10
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#ifdef CONFIG_SMP
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/*
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* Get the number of CPU cores from the SCU configuration
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*/
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unsigned int __init scu_get_core_count(void __iomem *scu_base)
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{
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unsigned int ncores = readl_relaxed(scu_base + SCU_CONFIG);
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return (ncores & 0x03) + 1;
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}
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/*
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* Enable the SCU
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*/
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void scu_enable(void __iomem *scu_base)
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{
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u32 scu_ctrl;
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#ifdef CONFIG_ARM_ERRATA_764369
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/* Cortex-A9 only */
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if ((read_cpuid_id() & 0xff0ffff0) == 0x410fc090) {
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scu_ctrl = readl_relaxed(scu_base + 0x30);
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if (!(scu_ctrl & 1))
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writel_relaxed(scu_ctrl | 0x1, scu_base + 0x30);
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}
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#endif
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scu_ctrl = readl_relaxed(scu_base + SCU_CTRL);
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/* already enabled? */
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if (scu_ctrl & 1)
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return;
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scu_ctrl |= 1;
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writel_relaxed(scu_ctrl, scu_base + SCU_CTRL);
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/*
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* Ensure that the data accessed by CPU0 before the SCU was
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* initialised is visible to the other CPUs.
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*/
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flush_cache_all();
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}
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#endif
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/*
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* Set the executing CPUs power mode as defined. This will be in
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* preparation for it executing a WFI instruction.
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*
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* This function must be called with preemption disabled, and as it
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* has the side effect of disabling coherency, caches must have been
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* flushed. Interrupts must also have been disabled.
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*/
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int scu_power_mode(void __iomem *scu_base, unsigned int mode)
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{
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unsigned int val;
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int cpu = MPIDR_AFFINITY_LEVEL(cpu_logical_map(smp_processor_id()), 0);
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if (mode > 3 || mode == 1 || cpu > 3)
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return -EINVAL;
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val = readb_relaxed(scu_base + SCU_CPU_STATUS + cpu) & ~0x03;
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val |= mode;
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writeb_relaxed(val, scu_base + SCU_CPU_STATUS + cpu);
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return 0;
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}
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