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d561514f61
sis900 defines 'cfgpmcsr' as an I/O space register, but CFGPMCSR is in fact a config space register, and there is no register at offset 0x44 in I/O space, so delete the enum. Signed-off-by: Lennert Buytenhek <buytenh@wantstofly.org> Signed-off-by: Jeff Garzik <jgarzik@pobox.com>
324 lines
10 KiB
C
324 lines
10 KiB
C
/* sis900.h Definitions for SiS ethernet controllers including 7014/7016 and 900
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* Copyright 1999 Silicon Integrated System Corporation
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* References:
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* SiS 7016 Fast Ethernet PCI Bus 10/100 Mbps LAN Controller with OnNow Support,
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* preliminary Rev. 1.0 Jan. 14, 1998
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* SiS 900 Fast Ethernet PCI Bus 10/100 Mbps LAN Single Chip with OnNow Support,
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* preliminary Rev. 1.0 Nov. 10, 1998
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* SiS 7014 Single Chip 100BASE-TX/10BASE-T Physical Layer Solution,
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* preliminary Rev. 1.0 Jan. 18, 1998
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* http://www.sis.com.tw/support/databook.htm
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*/
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/*
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* SiS 7016 and SiS 900 ethernet controller registers
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*/
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/* The I/O extent, SiS 900 needs 256 bytes of io address */
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#define SIS900_TOTAL_SIZE 0x100
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/* Symbolic offsets to registers. */
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enum sis900_registers {
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cr=0x0, //Command Register
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cfg=0x4, //Configuration Register
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mear=0x8, //EEPROM Access Register
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ptscr=0xc, //PCI Test Control Register
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isr=0x10, //Interrupt Status Register
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imr=0x14, //Interrupt Mask Register
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ier=0x18, //Interrupt Enable Register
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epar=0x18, //Enhanced PHY Access Register
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txdp=0x20, //Transmit Descriptor Pointer Register
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txcfg=0x24, //Transmit Configuration Register
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rxdp=0x30, //Receive Descriptor Pointer Register
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rxcfg=0x34, //Receive Configuration Register
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flctrl=0x38, //Flow Control Register
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rxlen=0x3c, //Receive Packet Length Register
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rfcr=0x48, //Receive Filter Control Register
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rfdr=0x4C, //Receive Filter Data Register
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pmctrl=0xB0, //Power Management Control Register
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pmer=0xB4 //Power Management Wake-up Event Register
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};
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/* Symbolic names for bits in various registers */
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enum sis900_command_register_bits {
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RELOAD = 0x00000400, ACCESSMODE = 0x00000200,/* ET */
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RESET = 0x00000100, SWI = 0x00000080, RxRESET = 0x00000020,
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TxRESET = 0x00000010, RxDIS = 0x00000008, RxENA = 0x00000004,
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TxDIS = 0x00000002, TxENA = 0x00000001
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};
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enum sis900_configuration_register_bits {
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DESCRFMT = 0x00000100 /* 7016 specific */, REQALG = 0x00000080,
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SB = 0x00000040, POW = 0x00000020, EXD = 0x00000010,
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PESEL = 0x00000008, LPM = 0x00000004, BEM = 0x00000001,
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/* 635 & 900B Specific */
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RND_CNT = 0x00000400, FAIR_BACKOFF = 0x00000200,
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EDB_MASTER_EN = 0x00002000
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};
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enum sis900_eeprom_access_reigster_bits {
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MDC = 0x00000040, MDDIR = 0x00000020, MDIO = 0x00000010, /* 7016 specific */
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EECS = 0x00000008, EECLK = 0x00000004, EEDO = 0x00000002,
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EEDI = 0x00000001
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};
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enum sis900_interrupt_register_bits {
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WKEVT = 0x10000000, TxPAUSEEND = 0x08000000, TxPAUSE = 0x04000000,
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TxRCMP = 0x02000000, RxRCMP = 0x01000000, DPERR = 0x00800000,
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SSERR = 0x00400000, RMABT = 0x00200000, RTABT = 0x00100000,
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RxSOVR = 0x00010000, HIBERR = 0x00008000, SWINT = 0x00001000,
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MIBINT = 0x00000800, TxURN = 0x00000400, TxIDLE = 0x00000200,
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TxERR = 0x00000100, TxDESC = 0x00000080, TxOK = 0x00000040,
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RxORN = 0x00000020, RxIDLE = 0x00000010, RxEARLY = 0x00000008,
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RxERR = 0x00000004, RxDESC = 0x00000002, RxOK = 0x00000001
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};
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enum sis900_interrupt_enable_reigster_bits {
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IE = 0x00000001
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};
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/* maximum dma burst for transmission and receive */
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#define MAX_DMA_RANGE 7 /* actually 0 means MAXIMUM !! */
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#define TxMXDMA_shift 20
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#define RxMXDMA_shift 20
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enum sis900_tx_rx_dma{
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DMA_BURST_512 = 0, DMA_BURST_64 = 5
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};
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/* transmit FIFO thresholds */
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#define TX_FILL_THRESH 16 /* 1/4 FIFO size */
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#define TxFILLT_shift 8
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#define TxDRNT_shift 0
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#define TxDRNT_100 48 /* 3/4 FIFO size */
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#define TxDRNT_10 16 /* 1/2 FIFO size */
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enum sis900_transmit_config_register_bits {
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TxCSI = 0x80000000, TxHBI = 0x40000000, TxMLB = 0x20000000,
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TxATP = 0x10000000, TxIFG = 0x0C000000, TxFILLT = 0x00003F00,
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TxDRNT = 0x0000003F
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};
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/* recevie FIFO thresholds */
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#define RxDRNT_shift 1
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#define RxDRNT_100 16 /* 1/2 FIFO size */
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#define RxDRNT_10 24 /* 3/4 FIFO size */
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enum sis900_reveive_config_register_bits {
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RxAEP = 0x80000000, RxARP = 0x40000000, RxATX = 0x10000000,
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RxAJAB = 0x08000000, RxDRNT = 0x0000007F
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};
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#define RFAA_shift 28
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#define RFADDR_shift 16
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enum sis900_receive_filter_control_register_bits {
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RFEN = 0x80000000, RFAAB = 0x40000000, RFAAM = 0x20000000,
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RFAAP = 0x10000000, RFPromiscuous = (RFAAB|RFAAM|RFAAP)
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};
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enum sis900_reveive_filter_data_mask {
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RFDAT = 0x0000FFFF
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};
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/* EEPROM Addresses */
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enum sis900_eeprom_address {
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EEPROMSignature = 0x00, EEPROMVendorID = 0x02, EEPROMDeviceID = 0x03,
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EEPROMMACAddr = 0x08, EEPROMChecksum = 0x0b
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};
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/* The EEPROM commands include the alway-set leading bit. Refer to NM93Cxx datasheet */
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enum sis900_eeprom_command {
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EEread = 0x0180, EEwrite = 0x0140, EEerase = 0x01C0,
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EEwriteEnable = 0x0130, EEwriteDisable = 0x0100,
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EEeraseAll = 0x0120, EEwriteAll = 0x0110,
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EEaddrMask = 0x013F, EEcmdShift = 16
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};
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/* For SiS962 or SiS963, request the eeprom software access */
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enum sis96x_eeprom_command {
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EEREQ = 0x00000400, EEDONE = 0x00000200, EEGNT = 0x00000100
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};
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/* PCI Registers */
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enum sis900_pci_registers {
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CFGPMC = 0x40,
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CFGPMCSR = 0x44
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};
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/* Power management capabilities bits */
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enum sis900_cfgpmc_register_bits {
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PMVER = 0x00070000,
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DSI = 0x00100000,
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PMESP = 0xf8000000
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};
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enum sis900_pmesp_bits {
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PME_D0 = 0x1,
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PME_D1 = 0x2,
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PME_D2 = 0x4,
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PME_D3H = 0x8,
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PME_D3C = 0x10
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};
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/* Power management control/status bits */
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enum sis900_cfgpmcsr_register_bits {
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PMESTS = 0x00004000,
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PME_EN = 0x00000100, // Power management enable
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PWR_STA = 0x00000003 // Current power state
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};
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/* Wake-on-LAN support. */
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enum sis900_power_management_control_register_bits {
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LINKLOSS = 0x00000001,
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LINKON = 0x00000002,
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MAGICPKT = 0x00000400,
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ALGORITHM = 0x00000800,
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FRM1EN = 0x00100000,
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FRM2EN = 0x00200000,
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FRM3EN = 0x00400000,
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FRM1ACS = 0x01000000,
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FRM2ACS = 0x02000000,
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FRM3ACS = 0x04000000,
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WAKEALL = 0x40000000,
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GATECLK = 0x80000000
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};
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/* Management Data I/O (mdio) frame */
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#define MIIread 0x6000
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#define MIIwrite 0x5002
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#define MIIpmdShift 7
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#define MIIregShift 2
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#define MIIcmdLen 16
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#define MIIcmdShift 16
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/* Buffer Descriptor Status*/
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enum sis900_buffer_status {
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OWN = 0x80000000, MORE = 0x40000000, INTR = 0x20000000,
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SUPCRC = 0x10000000, INCCRC = 0x10000000,
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OK = 0x08000000, DSIZE = 0x00000FFF
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};
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/* Status for TX Buffers */
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enum sis900_tx_buffer_status {
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ABORT = 0x04000000, UNDERRUN = 0x02000000, NOCARRIER = 0x01000000,
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DEFERD = 0x00800000, EXCDEFER = 0x00400000, OWCOLL = 0x00200000,
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EXCCOLL = 0x00100000, COLCNT = 0x000F0000
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};
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enum sis900_rx_bufer_status {
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OVERRUN = 0x02000000, DEST = 0x00800000, BCAST = 0x01800000,
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MCAST = 0x01000000, UNIMATCH = 0x00800000, TOOLONG = 0x00400000,
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RUNT = 0x00200000, RXISERR = 0x00100000, CRCERR = 0x00080000,
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FAERR = 0x00040000, LOOPBK = 0x00020000, RXCOL = 0x00010000
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};
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/* MII register offsets */
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enum mii_registers {
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MII_CONTROL = 0x0000, MII_STATUS = 0x0001, MII_PHY_ID0 = 0x0002,
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MII_PHY_ID1 = 0x0003, MII_ANADV = 0x0004, MII_ANLPAR = 0x0005,
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MII_ANEXT = 0x0006
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};
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/* mii registers specific to SiS 900 */
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enum sis_mii_registers {
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MII_CONFIG1 = 0x0010, MII_CONFIG2 = 0x0011, MII_STSOUT = 0x0012,
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MII_MASK = 0x0013, MII_RESV = 0x0014
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};
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/* mii registers specific to ICS 1893 */
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enum ics_mii_registers {
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MII_EXTCTRL = 0x0010, MII_QPDSTS = 0x0011, MII_10BTOP = 0x0012,
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MII_EXTCTRL2 = 0x0013
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};
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/* mii registers specific to AMD 79C901 */
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enum amd_mii_registers {
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MII_STATUS_SUMMARY = 0x0018
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};
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/* MII Control register bit definitions. */
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enum mii_control_register_bits {
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MII_CNTL_FDX = 0x0100, MII_CNTL_RST_AUTO = 0x0200,
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MII_CNTL_ISOLATE = 0x0400, MII_CNTL_PWRDWN = 0x0800,
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MII_CNTL_AUTO = 0x1000, MII_CNTL_SPEED = 0x2000,
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MII_CNTL_LPBK = 0x4000, MII_CNTL_RESET = 0x8000
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};
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/* MII Status register bit */
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enum mii_status_register_bits {
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MII_STAT_EXT = 0x0001, MII_STAT_JAB = 0x0002,
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MII_STAT_LINK = 0x0004, MII_STAT_CAN_AUTO = 0x0008,
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MII_STAT_FAULT = 0x0010, MII_STAT_AUTO_DONE = 0x0020,
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MII_STAT_CAN_T = 0x0800, MII_STAT_CAN_T_FDX = 0x1000,
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MII_STAT_CAN_TX = 0x2000, MII_STAT_CAN_TX_FDX = 0x4000,
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MII_STAT_CAN_T4 = 0x8000
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};
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#define MII_ID1_OUI_LO 0xFC00 /* low bits of OUI mask */
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#define MII_ID1_MODEL 0x03F0 /* model number */
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#define MII_ID1_REV 0x000F /* model number */
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/* MII NWAY Register Bits ...
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valid for the ANAR (Auto-Negotiation Advertisement) and
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ANLPAR (Auto-Negotiation Link Partner) registers */
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enum mii_nway_register_bits {
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MII_NWAY_NODE_SEL = 0x001f, MII_NWAY_CSMA_CD = 0x0001,
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MII_NWAY_T = 0x0020, MII_NWAY_T_FDX = 0x0040,
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MII_NWAY_TX = 0x0080, MII_NWAY_TX_FDX = 0x0100,
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MII_NWAY_T4 = 0x0200, MII_NWAY_PAUSE = 0x0400,
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MII_NWAY_RF = 0x2000, MII_NWAY_ACK = 0x4000,
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MII_NWAY_NP = 0x8000
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};
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enum mii_stsout_register_bits {
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MII_STSOUT_LINK_FAIL = 0x4000,
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MII_STSOUT_SPD = 0x0080, MII_STSOUT_DPLX = 0x0040
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};
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enum mii_stsics_register_bits {
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MII_STSICS_SPD = 0x8000, MII_STSICS_DPLX = 0x4000,
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MII_STSICS_LINKSTS = 0x0001
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};
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enum mii_stssum_register_bits {
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MII_STSSUM_LINK = 0x0008, MII_STSSUM_DPLX = 0x0004,
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MII_STSSUM_AUTO = 0x0002, MII_STSSUM_SPD = 0x0001
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};
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enum sis900_revision_id {
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SIS630A_900_REV = 0x80, SIS630E_900_REV = 0x81,
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SIS630S_900_REV = 0x82, SIS630EA1_900_REV = 0x83,
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SIS630ET_900_REV = 0x84, SIS635A_900_REV = 0x90,
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SIS96x_900_REV = 0X91, SIS900B_900_REV = 0x03
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};
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enum sis630_revision_id {
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SIS630A0 = 0x00, SIS630A1 = 0x01,
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SIS630B0 = 0x10, SIS630B1 = 0x11
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};
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#define FDX_CAPABLE_DUPLEX_UNKNOWN 0
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#define FDX_CAPABLE_HALF_SELECTED 1
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#define FDX_CAPABLE_FULL_SELECTED 2
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#define HW_SPEED_UNCONFIG 0
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#define HW_SPEED_HOME 1
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#define HW_SPEED_10_MBPS 10
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#define HW_SPEED_100_MBPS 100
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#define HW_SPEED_DEFAULT (HW_SPEED_100_MBPS)
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#define CRC_SIZE 4
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#define MAC_HEADER_SIZE 14
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#define TX_BUF_SIZE 1536
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#define RX_BUF_SIZE 1536
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#define NUM_TX_DESC 16 /* Number of Tx descriptor registers. */
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#define NUM_RX_DESC 16 /* Number of Rx descriptor registers. */
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#define TX_TOTAL_SIZE NUM_TX_DESC*sizeof(BufferDesc)
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#define RX_TOTAL_SIZE NUM_RX_DESC*sizeof(BufferDesc)
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/* PCI stuff, should be move to pci.h */
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#define SIS630_VENDOR_ID 0x1039
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#define SIS630_DEVICE_ID 0x0630
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