mirror of
https://github.com/edk2-porting/linux-next.git
synced 2024-12-17 17:53:56 +08:00
a76053707d
Most users of ndo_do_ioctl are ethernet drivers that implement the MII commands SIOCGMIIPHY/SIOCGMIIREG/SIOCSMIIREG, or hardware timestamping with SIOCSHWTSTAMP/SIOCGHWTSTAMP. Separate these from the few drivers that use ndo_do_ioctl to implement SIOCBOND, SIOCBR and SIOCWANDEV commands. This is a purely cosmetic change intended to help readers find their way through the implementation. Cc: Doug Ledford <dledford@redhat.com> Cc: Jason Gunthorpe <jgg@ziepe.ca> Cc: Jay Vosburgh <j.vosburgh@gmail.com> Cc: Veaceslav Falico <vfalico@gmail.com> Cc: Andy Gospodarek <andy@greyhouse.net> Cc: Andrew Lunn <andrew@lunn.ch> Cc: Vivien Didelot <vivien.didelot@gmail.com> Cc: Florian Fainelli <f.fainelli@gmail.com> Cc: Vladimir Oltean <olteanv@gmail.com> Cc: Leon Romanovsky <leon@kernel.org> Cc: linux-rdma@vger.kernel.org Signed-off-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Jason Gunthorpe <jgg@nvidia.com> Signed-off-by: David S. Miller <davem@davemloft.net>
736 lines
17 KiB
C
736 lines
17 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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*
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* Copyright (C) 2011 John Crispin <blogic@openwrt.org>
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*/
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#include <linux/kernel.h>
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#include <linux/slab.h>
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#include <linux/errno.h>
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#include <linux/types.h>
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#include <linux/interrupt.h>
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#include <linux/uaccess.h>
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#include <linux/in.h>
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#include <linux/netdevice.h>
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#include <linux/etherdevice.h>
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#include <linux/phy.h>
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#include <linux/ip.h>
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#include <linux/tcp.h>
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#include <linux/skbuff.h>
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#include <linux/mm.h>
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#include <linux/platform_device.h>
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#include <linux/ethtool.h>
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#include <linux/init.h>
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#include <linux/delay.h>
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#include <linux/io.h>
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#include <linux/dma-mapping.h>
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#include <linux/module.h>
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#include <asm/checksum.h>
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#include <lantiq_soc.h>
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#include <xway_dma.h>
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#include <lantiq_platform.h>
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#define LTQ_ETOP_MDIO 0x11804
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#define MDIO_REQUEST 0x80000000
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#define MDIO_READ 0x40000000
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#define MDIO_ADDR_MASK 0x1f
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#define MDIO_ADDR_OFFSET 0x15
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#define MDIO_REG_MASK 0x1f
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#define MDIO_REG_OFFSET 0x10
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#define MDIO_VAL_MASK 0xffff
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#define PPE32_CGEN 0x800
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#define LQ_PPE32_ENET_MAC_CFG 0x1840
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#define LTQ_ETOP_ENETS0 0x11850
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#define LTQ_ETOP_MAC_DA0 0x1186C
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#define LTQ_ETOP_MAC_DA1 0x11870
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#define LTQ_ETOP_CFG 0x16020
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#define LTQ_ETOP_IGPLEN 0x16080
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#define MAX_DMA_CHAN 0x8
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#define MAX_DMA_CRC_LEN 0x4
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#define MAX_DMA_DATA_LEN 0x600
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#define ETOP_FTCU BIT(28)
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#define ETOP_MII_MASK 0xf
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#define ETOP_MII_NORMAL 0xd
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#define ETOP_MII_REVERSE 0xe
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#define ETOP_PLEN_UNDER 0x40
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#define ETOP_CGEN 0x800
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/* use 2 static channels for TX/RX */
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#define LTQ_ETOP_TX_CHANNEL 1
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#define LTQ_ETOP_RX_CHANNEL 6
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#define IS_TX(x) (x == LTQ_ETOP_TX_CHANNEL)
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#define IS_RX(x) (x == LTQ_ETOP_RX_CHANNEL)
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#define ltq_etop_r32(x) ltq_r32(ltq_etop_membase + (x))
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#define ltq_etop_w32(x, y) ltq_w32(x, ltq_etop_membase + (y))
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#define ltq_etop_w32_mask(x, y, z) \
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ltq_w32_mask(x, y, ltq_etop_membase + (z))
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#define DRV_VERSION "1.0"
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static void __iomem *ltq_etop_membase;
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struct ltq_etop_chan {
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int idx;
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int tx_free;
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struct net_device *netdev;
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struct napi_struct napi;
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struct ltq_dma_channel dma;
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struct sk_buff *skb[LTQ_DESC_NUM];
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};
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struct ltq_etop_priv {
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struct net_device *netdev;
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struct platform_device *pdev;
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struct ltq_eth_data *pldata;
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struct resource *res;
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struct mii_bus *mii_bus;
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struct ltq_etop_chan ch[MAX_DMA_CHAN];
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int tx_free[MAX_DMA_CHAN >> 1];
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spinlock_t lock;
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};
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static int
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ltq_etop_alloc_skb(struct ltq_etop_chan *ch)
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{
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struct ltq_etop_priv *priv = netdev_priv(ch->netdev);
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ch->skb[ch->dma.desc] = netdev_alloc_skb(ch->netdev, MAX_DMA_DATA_LEN);
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if (!ch->skb[ch->dma.desc])
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return -ENOMEM;
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ch->dma.desc_base[ch->dma.desc].addr = dma_map_single(&priv->pdev->dev,
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ch->skb[ch->dma.desc]->data, MAX_DMA_DATA_LEN,
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DMA_FROM_DEVICE);
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ch->dma.desc_base[ch->dma.desc].addr =
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CPHYSADDR(ch->skb[ch->dma.desc]->data);
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ch->dma.desc_base[ch->dma.desc].ctl =
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LTQ_DMA_OWN | LTQ_DMA_RX_OFFSET(NET_IP_ALIGN) |
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MAX_DMA_DATA_LEN;
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skb_reserve(ch->skb[ch->dma.desc], NET_IP_ALIGN);
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return 0;
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}
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static void
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ltq_etop_hw_receive(struct ltq_etop_chan *ch)
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{
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struct ltq_etop_priv *priv = netdev_priv(ch->netdev);
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struct ltq_dma_desc *desc = &ch->dma.desc_base[ch->dma.desc];
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struct sk_buff *skb = ch->skb[ch->dma.desc];
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int len = (desc->ctl & LTQ_DMA_SIZE_MASK) - MAX_DMA_CRC_LEN;
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unsigned long flags;
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spin_lock_irqsave(&priv->lock, flags);
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if (ltq_etop_alloc_skb(ch)) {
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netdev_err(ch->netdev,
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"failed to allocate new rx buffer, stopping DMA\n");
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ltq_dma_close(&ch->dma);
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}
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ch->dma.desc++;
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ch->dma.desc %= LTQ_DESC_NUM;
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spin_unlock_irqrestore(&priv->lock, flags);
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skb_put(skb, len);
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skb->protocol = eth_type_trans(skb, ch->netdev);
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netif_receive_skb(skb);
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}
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static int
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ltq_etop_poll_rx(struct napi_struct *napi, int budget)
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{
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struct ltq_etop_chan *ch = container_of(napi,
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struct ltq_etop_chan, napi);
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int work_done = 0;
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while (work_done < budget) {
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struct ltq_dma_desc *desc = &ch->dma.desc_base[ch->dma.desc];
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if ((desc->ctl & (LTQ_DMA_OWN | LTQ_DMA_C)) != LTQ_DMA_C)
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break;
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ltq_etop_hw_receive(ch);
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work_done++;
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}
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if (work_done < budget) {
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napi_complete_done(&ch->napi, work_done);
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ltq_dma_ack_irq(&ch->dma);
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}
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return work_done;
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}
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static int
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ltq_etop_poll_tx(struct napi_struct *napi, int budget)
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{
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struct ltq_etop_chan *ch =
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container_of(napi, struct ltq_etop_chan, napi);
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struct ltq_etop_priv *priv = netdev_priv(ch->netdev);
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struct netdev_queue *txq =
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netdev_get_tx_queue(ch->netdev, ch->idx >> 1);
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unsigned long flags;
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spin_lock_irqsave(&priv->lock, flags);
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while ((ch->dma.desc_base[ch->tx_free].ctl &
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(LTQ_DMA_OWN | LTQ_DMA_C)) == LTQ_DMA_C) {
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dev_kfree_skb_any(ch->skb[ch->tx_free]);
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ch->skb[ch->tx_free] = NULL;
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memset(&ch->dma.desc_base[ch->tx_free], 0,
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sizeof(struct ltq_dma_desc));
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ch->tx_free++;
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ch->tx_free %= LTQ_DESC_NUM;
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}
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spin_unlock_irqrestore(&priv->lock, flags);
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if (netif_tx_queue_stopped(txq))
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netif_tx_start_queue(txq);
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napi_complete(&ch->napi);
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ltq_dma_ack_irq(&ch->dma);
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return 1;
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}
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static irqreturn_t
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ltq_etop_dma_irq(int irq, void *_priv)
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{
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struct ltq_etop_priv *priv = _priv;
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int ch = irq - LTQ_DMA_CH0_INT;
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napi_schedule(&priv->ch[ch].napi);
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return IRQ_HANDLED;
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}
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static void
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ltq_etop_free_channel(struct net_device *dev, struct ltq_etop_chan *ch)
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{
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struct ltq_etop_priv *priv = netdev_priv(dev);
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ltq_dma_free(&ch->dma);
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if (ch->dma.irq)
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free_irq(ch->dma.irq, priv);
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if (IS_RX(ch->idx)) {
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int desc;
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for (desc = 0; desc < LTQ_DESC_NUM; desc++)
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dev_kfree_skb_any(ch->skb[ch->dma.desc]);
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}
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}
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static void
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ltq_etop_hw_exit(struct net_device *dev)
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{
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struct ltq_etop_priv *priv = netdev_priv(dev);
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int i;
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ltq_pmu_disable(PMU_PPE);
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for (i = 0; i < MAX_DMA_CHAN; i++)
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if (IS_TX(i) || IS_RX(i))
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ltq_etop_free_channel(dev, &priv->ch[i]);
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}
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static int
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ltq_etop_hw_init(struct net_device *dev)
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{
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struct ltq_etop_priv *priv = netdev_priv(dev);
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int i;
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ltq_pmu_enable(PMU_PPE);
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switch (priv->pldata->mii_mode) {
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case PHY_INTERFACE_MODE_RMII:
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ltq_etop_w32_mask(ETOP_MII_MASK,
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ETOP_MII_REVERSE, LTQ_ETOP_CFG);
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break;
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case PHY_INTERFACE_MODE_MII:
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ltq_etop_w32_mask(ETOP_MII_MASK,
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ETOP_MII_NORMAL, LTQ_ETOP_CFG);
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break;
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default:
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netdev_err(dev, "unknown mii mode %d\n",
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priv->pldata->mii_mode);
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return -ENOTSUPP;
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}
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/* enable crc generation */
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ltq_etop_w32(PPE32_CGEN, LQ_PPE32_ENET_MAC_CFG);
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ltq_dma_init_port(DMA_PORT_ETOP);
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for (i = 0; i < MAX_DMA_CHAN; i++) {
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int irq = LTQ_DMA_CH0_INT + i;
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struct ltq_etop_chan *ch = &priv->ch[i];
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ch->idx = ch->dma.nr = i;
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ch->dma.dev = &priv->pdev->dev;
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if (IS_TX(i)) {
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ltq_dma_alloc_tx(&ch->dma);
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request_irq(irq, ltq_etop_dma_irq, 0, "etop_tx", priv);
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} else if (IS_RX(i)) {
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ltq_dma_alloc_rx(&ch->dma);
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for (ch->dma.desc = 0; ch->dma.desc < LTQ_DESC_NUM;
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ch->dma.desc++)
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if (ltq_etop_alloc_skb(ch))
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return -ENOMEM;
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ch->dma.desc = 0;
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request_irq(irq, ltq_etop_dma_irq, 0, "etop_rx", priv);
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}
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ch->dma.irq = irq;
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}
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return 0;
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}
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static void
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ltq_etop_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
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{
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strlcpy(info->driver, "Lantiq ETOP", sizeof(info->driver));
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strlcpy(info->bus_info, "internal", sizeof(info->bus_info));
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strlcpy(info->version, DRV_VERSION, sizeof(info->version));
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}
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static const struct ethtool_ops ltq_etop_ethtool_ops = {
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.get_drvinfo = ltq_etop_get_drvinfo,
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.nway_reset = phy_ethtool_nway_reset,
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.get_link_ksettings = phy_ethtool_get_link_ksettings,
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.set_link_ksettings = phy_ethtool_set_link_ksettings,
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};
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static int
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ltq_etop_mdio_wr(struct mii_bus *bus, int phy_addr, int phy_reg, u16 phy_data)
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{
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u32 val = MDIO_REQUEST |
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((phy_addr & MDIO_ADDR_MASK) << MDIO_ADDR_OFFSET) |
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((phy_reg & MDIO_REG_MASK) << MDIO_REG_OFFSET) |
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phy_data;
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while (ltq_etop_r32(LTQ_ETOP_MDIO) & MDIO_REQUEST)
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;
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ltq_etop_w32(val, LTQ_ETOP_MDIO);
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return 0;
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}
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static int
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ltq_etop_mdio_rd(struct mii_bus *bus, int phy_addr, int phy_reg)
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{
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u32 val = MDIO_REQUEST | MDIO_READ |
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((phy_addr & MDIO_ADDR_MASK) << MDIO_ADDR_OFFSET) |
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((phy_reg & MDIO_REG_MASK) << MDIO_REG_OFFSET);
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while (ltq_etop_r32(LTQ_ETOP_MDIO) & MDIO_REQUEST)
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;
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ltq_etop_w32(val, LTQ_ETOP_MDIO);
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while (ltq_etop_r32(LTQ_ETOP_MDIO) & MDIO_REQUEST)
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;
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val = ltq_etop_r32(LTQ_ETOP_MDIO) & MDIO_VAL_MASK;
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return val;
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}
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static void
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ltq_etop_mdio_link(struct net_device *dev)
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{
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/* nothing to do */
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}
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static int
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ltq_etop_mdio_probe(struct net_device *dev)
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{
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struct ltq_etop_priv *priv = netdev_priv(dev);
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struct phy_device *phydev;
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phydev = phy_find_first(priv->mii_bus);
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if (!phydev) {
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netdev_err(dev, "no PHY found\n");
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return -ENODEV;
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}
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phydev = phy_connect(dev, phydev_name(phydev),
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<q_etop_mdio_link, priv->pldata->mii_mode);
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if (IS_ERR(phydev)) {
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netdev_err(dev, "Could not attach to PHY\n");
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return PTR_ERR(phydev);
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}
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phy_set_max_speed(phydev, SPEED_100);
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phy_attached_info(phydev);
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return 0;
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}
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static int
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ltq_etop_mdio_init(struct net_device *dev)
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{
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struct ltq_etop_priv *priv = netdev_priv(dev);
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int err;
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priv->mii_bus = mdiobus_alloc();
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if (!priv->mii_bus) {
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netdev_err(dev, "failed to allocate mii bus\n");
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err = -ENOMEM;
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goto err_out;
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}
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priv->mii_bus->priv = dev;
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priv->mii_bus->read = ltq_etop_mdio_rd;
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priv->mii_bus->write = ltq_etop_mdio_wr;
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priv->mii_bus->name = "ltq_mii";
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snprintf(priv->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
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priv->pdev->name, priv->pdev->id);
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if (mdiobus_register(priv->mii_bus)) {
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err = -ENXIO;
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goto err_out_free_mdiobus;
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}
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if (ltq_etop_mdio_probe(dev)) {
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err = -ENXIO;
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goto err_out_unregister_bus;
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}
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return 0;
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err_out_unregister_bus:
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mdiobus_unregister(priv->mii_bus);
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err_out_free_mdiobus:
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mdiobus_free(priv->mii_bus);
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err_out:
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return err;
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}
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static void
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ltq_etop_mdio_cleanup(struct net_device *dev)
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{
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struct ltq_etop_priv *priv = netdev_priv(dev);
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phy_disconnect(dev->phydev);
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mdiobus_unregister(priv->mii_bus);
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mdiobus_free(priv->mii_bus);
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}
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static int
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ltq_etop_open(struct net_device *dev)
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{
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struct ltq_etop_priv *priv = netdev_priv(dev);
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int i;
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for (i = 0; i < MAX_DMA_CHAN; i++) {
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struct ltq_etop_chan *ch = &priv->ch[i];
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if (!IS_TX(i) && (!IS_RX(i)))
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continue;
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ltq_dma_open(&ch->dma);
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ltq_dma_enable_irq(&ch->dma);
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napi_enable(&ch->napi);
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}
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phy_start(dev->phydev);
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netif_tx_start_all_queues(dev);
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return 0;
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}
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static int
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ltq_etop_stop(struct net_device *dev)
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{
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struct ltq_etop_priv *priv = netdev_priv(dev);
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int i;
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netif_tx_stop_all_queues(dev);
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phy_stop(dev->phydev);
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for (i = 0; i < MAX_DMA_CHAN; i++) {
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struct ltq_etop_chan *ch = &priv->ch[i];
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if (!IS_RX(i) && !IS_TX(i))
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continue;
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napi_disable(&ch->napi);
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ltq_dma_close(&ch->dma);
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}
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return 0;
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}
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static int
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ltq_etop_tx(struct sk_buff *skb, struct net_device *dev)
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{
|
|
int queue = skb_get_queue_mapping(skb);
|
|
struct netdev_queue *txq = netdev_get_tx_queue(dev, queue);
|
|
struct ltq_etop_priv *priv = netdev_priv(dev);
|
|
struct ltq_etop_chan *ch = &priv->ch[(queue << 1) | 1];
|
|
struct ltq_dma_desc *desc = &ch->dma.desc_base[ch->dma.desc];
|
|
int len;
|
|
unsigned long flags;
|
|
u32 byte_offset;
|
|
|
|
len = skb->len < ETH_ZLEN ? ETH_ZLEN : skb->len;
|
|
|
|
if ((desc->ctl & (LTQ_DMA_OWN | LTQ_DMA_C)) || ch->skb[ch->dma.desc]) {
|
|
dev_kfree_skb_any(skb);
|
|
netdev_err(dev, "tx ring full\n");
|
|
netif_tx_stop_queue(txq);
|
|
return NETDEV_TX_BUSY;
|
|
}
|
|
|
|
/* dma needs to start on a 16 byte aligned address */
|
|
byte_offset = CPHYSADDR(skb->data) % 16;
|
|
ch->skb[ch->dma.desc] = skb;
|
|
|
|
netif_trans_update(dev);
|
|
|
|
spin_lock_irqsave(&priv->lock, flags);
|
|
desc->addr = ((unsigned int) dma_map_single(&priv->pdev->dev, skb->data, len,
|
|
DMA_TO_DEVICE)) - byte_offset;
|
|
wmb();
|
|
desc->ctl = LTQ_DMA_OWN | LTQ_DMA_SOP | LTQ_DMA_EOP |
|
|
LTQ_DMA_TX_OFFSET(byte_offset) | (len & LTQ_DMA_SIZE_MASK);
|
|
ch->dma.desc++;
|
|
ch->dma.desc %= LTQ_DESC_NUM;
|
|
spin_unlock_irqrestore(&priv->lock, flags);
|
|
|
|
if (ch->dma.desc_base[ch->dma.desc].ctl & LTQ_DMA_OWN)
|
|
netif_tx_stop_queue(txq);
|
|
|
|
return NETDEV_TX_OK;
|
|
}
|
|
|
|
static int
|
|
ltq_etop_change_mtu(struct net_device *dev, int new_mtu)
|
|
{
|
|
struct ltq_etop_priv *priv = netdev_priv(dev);
|
|
unsigned long flags;
|
|
|
|
dev->mtu = new_mtu;
|
|
|
|
spin_lock_irqsave(&priv->lock, flags);
|
|
ltq_etop_w32((ETOP_PLEN_UNDER << 16) | new_mtu, LTQ_ETOP_IGPLEN);
|
|
spin_unlock_irqrestore(&priv->lock, flags);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int
|
|
ltq_etop_set_mac_address(struct net_device *dev, void *p)
|
|
{
|
|
int ret = eth_mac_addr(dev, p);
|
|
|
|
if (!ret) {
|
|
struct ltq_etop_priv *priv = netdev_priv(dev);
|
|
unsigned long flags;
|
|
|
|
/* store the mac for the unicast filter */
|
|
spin_lock_irqsave(&priv->lock, flags);
|
|
ltq_etop_w32(*((u32 *)dev->dev_addr), LTQ_ETOP_MAC_DA0);
|
|
ltq_etop_w32(*((u16 *)&dev->dev_addr[4]) << 16,
|
|
LTQ_ETOP_MAC_DA1);
|
|
spin_unlock_irqrestore(&priv->lock, flags);
|
|
}
|
|
return ret;
|
|
}
|
|
|
|
static void
|
|
ltq_etop_set_multicast_list(struct net_device *dev)
|
|
{
|
|
struct ltq_etop_priv *priv = netdev_priv(dev);
|
|
unsigned long flags;
|
|
|
|
/* ensure that the unicast filter is not enabled in promiscious mode */
|
|
spin_lock_irqsave(&priv->lock, flags);
|
|
if ((dev->flags & IFF_PROMISC) || (dev->flags & IFF_ALLMULTI))
|
|
ltq_etop_w32_mask(ETOP_FTCU, 0, LTQ_ETOP_ENETS0);
|
|
else
|
|
ltq_etop_w32_mask(0, ETOP_FTCU, LTQ_ETOP_ENETS0);
|
|
spin_unlock_irqrestore(&priv->lock, flags);
|
|
}
|
|
|
|
static int
|
|
ltq_etop_init(struct net_device *dev)
|
|
{
|
|
struct ltq_etop_priv *priv = netdev_priv(dev);
|
|
struct sockaddr mac;
|
|
int err;
|
|
bool random_mac = false;
|
|
|
|
dev->watchdog_timeo = 10 * HZ;
|
|
err = ltq_etop_hw_init(dev);
|
|
if (err)
|
|
goto err_hw;
|
|
ltq_etop_change_mtu(dev, 1500);
|
|
|
|
memcpy(&mac, &priv->pldata->mac, sizeof(struct sockaddr));
|
|
if (!is_valid_ether_addr(mac.sa_data)) {
|
|
pr_warn("etop: invalid MAC, using random\n");
|
|
eth_random_addr(mac.sa_data);
|
|
random_mac = true;
|
|
}
|
|
|
|
err = ltq_etop_set_mac_address(dev, &mac);
|
|
if (err)
|
|
goto err_netdev;
|
|
|
|
/* Set addr_assign_type here, ltq_etop_set_mac_address would reset it. */
|
|
if (random_mac)
|
|
dev->addr_assign_type = NET_ADDR_RANDOM;
|
|
|
|
ltq_etop_set_multicast_list(dev);
|
|
err = ltq_etop_mdio_init(dev);
|
|
if (err)
|
|
goto err_netdev;
|
|
return 0;
|
|
|
|
err_netdev:
|
|
unregister_netdev(dev);
|
|
free_netdev(dev);
|
|
err_hw:
|
|
ltq_etop_hw_exit(dev);
|
|
return err;
|
|
}
|
|
|
|
static void
|
|
ltq_etop_tx_timeout(struct net_device *dev, unsigned int txqueue)
|
|
{
|
|
int err;
|
|
|
|
ltq_etop_hw_exit(dev);
|
|
err = ltq_etop_hw_init(dev);
|
|
if (err)
|
|
goto err_hw;
|
|
netif_trans_update(dev);
|
|
netif_wake_queue(dev);
|
|
return;
|
|
|
|
err_hw:
|
|
ltq_etop_hw_exit(dev);
|
|
netdev_err(dev, "failed to restart etop after TX timeout\n");
|
|
}
|
|
|
|
static const struct net_device_ops ltq_eth_netdev_ops = {
|
|
.ndo_open = ltq_etop_open,
|
|
.ndo_stop = ltq_etop_stop,
|
|
.ndo_start_xmit = ltq_etop_tx,
|
|
.ndo_change_mtu = ltq_etop_change_mtu,
|
|
.ndo_eth_ioctl = phy_do_ioctl,
|
|
.ndo_set_mac_address = ltq_etop_set_mac_address,
|
|
.ndo_validate_addr = eth_validate_addr,
|
|
.ndo_set_rx_mode = ltq_etop_set_multicast_list,
|
|
.ndo_select_queue = dev_pick_tx_zero,
|
|
.ndo_init = ltq_etop_init,
|
|
.ndo_tx_timeout = ltq_etop_tx_timeout,
|
|
};
|
|
|
|
static int __init
|
|
ltq_etop_probe(struct platform_device *pdev)
|
|
{
|
|
struct net_device *dev;
|
|
struct ltq_etop_priv *priv;
|
|
struct resource *res;
|
|
int err;
|
|
int i;
|
|
|
|
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
|
if (!res) {
|
|
dev_err(&pdev->dev, "failed to get etop resource\n");
|
|
err = -ENOENT;
|
|
goto err_out;
|
|
}
|
|
|
|
res = devm_request_mem_region(&pdev->dev, res->start,
|
|
resource_size(res), dev_name(&pdev->dev));
|
|
if (!res) {
|
|
dev_err(&pdev->dev, "failed to request etop resource\n");
|
|
err = -EBUSY;
|
|
goto err_out;
|
|
}
|
|
|
|
ltq_etop_membase = devm_ioremap(&pdev->dev,
|
|
res->start, resource_size(res));
|
|
if (!ltq_etop_membase) {
|
|
dev_err(&pdev->dev, "failed to remap etop engine %d\n",
|
|
pdev->id);
|
|
err = -ENOMEM;
|
|
goto err_out;
|
|
}
|
|
|
|
dev = alloc_etherdev_mq(sizeof(struct ltq_etop_priv), 4);
|
|
if (!dev) {
|
|
err = -ENOMEM;
|
|
goto err_out;
|
|
}
|
|
strcpy(dev->name, "eth%d");
|
|
dev->netdev_ops = <q_eth_netdev_ops;
|
|
dev->ethtool_ops = <q_etop_ethtool_ops;
|
|
priv = netdev_priv(dev);
|
|
priv->res = res;
|
|
priv->pdev = pdev;
|
|
priv->pldata = dev_get_platdata(&pdev->dev);
|
|
priv->netdev = dev;
|
|
spin_lock_init(&priv->lock);
|
|
SET_NETDEV_DEV(dev, &pdev->dev);
|
|
|
|
for (i = 0; i < MAX_DMA_CHAN; i++) {
|
|
if (IS_TX(i))
|
|
netif_napi_add(dev, &priv->ch[i].napi,
|
|
ltq_etop_poll_tx, 8);
|
|
else if (IS_RX(i))
|
|
netif_napi_add(dev, &priv->ch[i].napi,
|
|
ltq_etop_poll_rx, 32);
|
|
priv->ch[i].netdev = dev;
|
|
}
|
|
|
|
err = register_netdev(dev);
|
|
if (err)
|
|
goto err_free;
|
|
|
|
platform_set_drvdata(pdev, dev);
|
|
return 0;
|
|
|
|
err_free:
|
|
free_netdev(dev);
|
|
err_out:
|
|
return err;
|
|
}
|
|
|
|
static int
|
|
ltq_etop_remove(struct platform_device *pdev)
|
|
{
|
|
struct net_device *dev = platform_get_drvdata(pdev);
|
|
|
|
if (dev) {
|
|
netif_tx_stop_all_queues(dev);
|
|
ltq_etop_hw_exit(dev);
|
|
ltq_etop_mdio_cleanup(dev);
|
|
unregister_netdev(dev);
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
static struct platform_driver ltq_mii_driver = {
|
|
.remove = ltq_etop_remove,
|
|
.driver = {
|
|
.name = "ltq_etop",
|
|
},
|
|
};
|
|
|
|
int __init
|
|
init_ltq_etop(void)
|
|
{
|
|
int ret = platform_driver_probe(<q_mii_driver, ltq_etop_probe);
|
|
|
|
if (ret)
|
|
pr_err("ltq_etop: Error registering platform driver!");
|
|
return ret;
|
|
}
|
|
|
|
static void __exit
|
|
exit_ltq_etop(void)
|
|
{
|
|
platform_driver_unregister(<q_mii_driver);
|
|
}
|
|
|
|
module_init(init_ltq_etop);
|
|
module_exit(exit_ltq_etop);
|
|
|
|
MODULE_AUTHOR("John Crispin <blogic@openwrt.org>");
|
|
MODULE_DESCRIPTION("Lantiq SoC ETOP");
|
|
MODULE_LICENSE("GPL");
|